filter.tan.qmsg

matlab在fpga中的应用的三个具体事例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "g_clk " "Info: Assuming node \"g_clk\" is an undefined clock" {  } { { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } } { "c:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "g_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "g_clk memory filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178 register accumulator:shift_add\|accum\[16\] 101.03 MHz 9.898 ns Internal " "Info: Clock \"g_clk\" has Internal fmax of 101.03 MHz between source memory \"filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178\" and destination register \"accumulator:shift_add\|accum\[16\]\" (period= 9.898 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.314 ns + Longest memory register " "Info: + Longest memory to register delay is 9.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.090 ns) 0.090 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178 1 MEM M4K_X73_Y68 1 " "Info: 1: + IC(0.000 ns) + CELL(0.090 ns) = 0.090 ns; Loc. = M4K_X73_Y68; Fanout = 1; MEM Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } "NODE_NAME" } } { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 3608 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.295 ns) + CELL(0.381 ns) 2.766 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~420 2 COMB LC_X66_Y52_N4 1 " "Info: 2: + IC(2.295 ns) + CELL(0.381 ns) = 2.766 ns; Loc. = LC_X66_Y52_N4; Fanout = 1; COMB Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~420'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.676 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 } "NODE_NAME" } } { "db/mux_8fb.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/mux_8fb.tdf" 138 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.244 ns) 3.625 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~422 3 COMB LC_X66_Y52_N3 1 " "Info: 3: + IC(0.615 ns) + CELL(0.244 ns) = 3.625 ns; Loc. = LC_X66_Y52_N3; Fanout = 1; COMB Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~422'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.859 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 } "NODE_NAME" } } { "db/mux_8fb.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/mux_8fb.tdf" 138 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.413 ns) + CELL(0.244 ns) 4.282 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~425 4 COMB LC_X66_Y52_N8 2 " "Info: 4: + IC(0.413 ns) + CELL(0.244 ns) = 4.282 ns; Loc. = LC_X66_Y52_N8; Fanout = 2; COMB Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|mux_8fb:mux2\|w_result1430w~425'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 } "NODE_NAME" } } { "db/mux_8fb.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/mux_8fb.tdf" 138 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.527 ns) 5.217 ns accumulator:shift_add\|accum\[4\]~COMBOUT 5 COMB LC_X66_Y52_N1 4 " "Info: 5: + IC(0.408 ns) + CELL(0.527 ns) = 5.217 ns; Loc. = LC_X66_Y52_N1; Fanout = 4; COMB Node = 'accumulator:shift_add\|accum\[4\]~COMBOUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.935 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 accumulator:shift_add|accum[4]~COMBOUT } "NODE_NAME" } } { "accumulator.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/accumulator.tdf" 31 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.509 ns) 6.897 ns accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[2\]~COUT 6 COMB LC_X59_Y52_N2 2 " "Info: 6: + IC(1.171 ns) + CELL(0.509 ns) = 6.897 ns; Loc. = LC_X59_Y52_N2; Fanout = 2; COMB Node = 'accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[2\]~COUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { accumulator:shift_add|accum[4]~COMBOUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT } "NODE_NAME" } } { "alt_stratix_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.tdf" 119 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.069 ns) 6.966 ns accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[3\]~COUT 7 COMB LC_X59_Y52_N3 2 " "Info: 7: + IC(0.000 ns) + CELL(0.069 ns) = 6.966 ns; Loc. = LC_X59_Y52_N3; Fanout = 2; COMB Node = 'accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[3\]~COUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.069 ns" { accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT } "NODE_NAME" } } { "alt_stratix_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.tdf" 119 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 7.121 ns accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[4\]~COUT 8 COMB LC_X59_Y52_N4 6 " "Info: 8: + IC(0.000 ns) + CELL(0.155 ns) = 7.121 ns; Loc. = LC_X59_Y52_N4; Fanout = 6; COMB Node = 'accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[4\]~COUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT } "NODE_NAME" } } { "alt_stratix_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.tdf" 119 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 7.299 ns accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[9\]~COUT 9 COMB LC_X59_Y52_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.178 ns) = 7.299 ns; Loc. = LC_X59_Y52_N9; Fanout = 6; COMB Node = 'accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|add_sub_cell\[9\]~COUT'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT } "NODE_NAME" } } { "alt_stratix_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.tdf" 119 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.566 ns) 7.865 ns accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|result\[14\] 10 COMB LC_X59_Y51_N4 1 " "Info: 10: + IC(0.000 ns) + CELL(0.566 ns) = 7.865 ns; Loc. = LC_X59_Y51_N4; Fanout = 1; COMB Node = 'accumulator:shift_add\|lpm_add_sub:adder\|alt_stratix_add_sub:stratix_adder\|result\[14\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] } "NODE_NAME" } } { "alt_stratix_add_sub.tdf" "" { Text "c:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.tdf" 103 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.346 ns) + CELL(0.103 ns) 9.314 ns accumulator:shift_add\|accum\[16\] 11 REG LC_X67_Y51_N9 4 " "Info: 11: + IC(1.346 ns) + CELL(0.103 ns) = 9.314 ns; Loc. = LC_X67_Y51_N9; Fanout = 4; REG Node = 'accumulator:shift_add\|accum\[16\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.449 ns" { accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] accumulator:shift_add|accum[16] } "NODE_NAME" } } { "accumulator.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/accumulator.tdf" 31 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 32.92 % ) " "Info: Total cell delay = 3.066 ns ( 32.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.248 ns ( 67.08 % ) " "Info: Total interconnect delay = 6.248 ns ( 67.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.314 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 accumulator:shift_add|accum[4]~COMBOUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] accumulator:shift_add|accum[16] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.314 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 accumulator:shift_add|accum[4]~COMBOUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] accumulator:shift_add|accum[16] } { 0.000ns 2.295ns 0.615ns 0.413ns 0.408ns 1.171ns 0.000ns 0.000ns 0.000ns 0.000ns 1.346ns } { 0.090ns 0.381ns 0.244ns 0.244ns 0.527ns 0.509ns 0.069ns 0.155ns 0.178ns 0.566ns 0.103ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.036 ns - Smallest " "Info: - Smallest clock skew is -0.036 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk destination 5.287 ns + Shortest register " "Info: + Shortest clock path from clock \"g_clk\" to destination register is 5.287 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns g_clk 1 CLK PIN_AA35 3774 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AA35; Fanout = 3774; CLK Node = 'g_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { g_clk } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.644 ns) + CELL(0.644 ns) 5.287 ns accumulator:shift_add\|accum\[16\] 2 REG LC_X67_Y51_N9 4 " "Info: 2: + IC(3.644 ns) + CELL(0.644 ns) = 5.287 ns; Loc. = LC_X67_Y51_N9; Fanout = 4; REG Node = 'accumulator:shift_add\|accum\[16\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.288 ns" { g_clk accumulator:shift_add|accum[16] } "NODE_NAME" } } { "accumulator.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/accumulator.tdf" 31 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 31.08 % ) " "Info: Total cell delay = 1.643 ns ( 31.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.644 ns ( 68.92 % ) " "Info: Total interconnect delay = 3.644 ns ( 68.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.287 ns" { g_clk accumulator:shift_add|accum[16] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.287 ns" { g_clk g_clk~out0 accumulator:shift_add|accum[16] } { 0.000ns 0.000ns 3.644ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk source 5.323 ns - Longest memory " "Info: - Longest clock path from clock \"g_clk\" to source memory is 5.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns g_clk 1 CLK PIN_AA35 3774 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AA35; Fanout = 3774; CLK Node = 'g_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { g_clk } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.685 ns) + CELL(0.639 ns) 5.323 ns filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178 2 MEM M4K_X73_Y68 1 " "Info: 2: + IC(3.685 ns) + CELL(0.639 ns) = 5.323 ns; Loc. = M4K_X73_Y68; Fanout = 1; MEM Node = 'filter_coef:rom_coef\|altsyncram:altsyncram_component\|altsyncram_v331:auto_generated\|ram_block1a178'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.324 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } "NODE_NAME" } } { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 3608 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.638 ns ( 30.77 % ) " "Info: Total cell delay = 1.638 ns ( 30.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.685 ns ( 69.23 % ) " "Info: Total interconnect delay = 3.685 ns ( 69.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.323 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.323 ns" { g_clk g_clk~out0 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } { 0.000ns 0.000ns 3.685ns } { 0.000ns 0.999ns 0.639ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.287 ns" { g_clk accumulator:shift_add|accum[16] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.287 ns" { g_clk g_clk~out0 accumulator:shift_add|accum[16] } { 0.000ns 0.000ns 3.644ns } { 0.000ns 0.999ns 0.644ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.323 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.323 ns" { g_clk g_clk~out0 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } { 0.000ns 0.000ns 3.685ns } { 0.000ns 0.999ns 0.639ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.537 ns + " "Info: + Micro clock to output delay of source is 0.537 ns" {  } { { "db/altsyncram_v331.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/db/altsyncram_v331.tdf" 3608 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "accumulator.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/accumulator.tdf" 31 6 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.314 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 accumulator:shift_add|accum[4]~COMBOUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] accumulator:shift_add|accum[16] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.314 ns" { filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~420 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~422 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|mux_8fb:mux2|w_result1430w~425 accumulator:shift_add|accum[4]~COMBOUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[14] accumulator:shift_add|accum[16] } { 0.000ns 2.295ns 0.615ns 0.413ns 0.408ns 1.171ns 0.000ns 0.000ns 0.000ns 0.000ns 1.346ns } { 0.090ns 0.381ns 0.244ns 0.244ns 0.527ns 0.509ns 0.069ns 0.155ns 0.178ns 0.566ns 0.103ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.287 ns" { g_clk accumulator:shift_add|accum[16] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.287 ns" { g_clk g_clk~out0 accumulator:shift_add|accum[16] } { 0.000ns 0.000ns 3.644ns } { 0.000ns 0.999ns 0.644ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.323 ns" { g_clk filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.323 ns" { g_clk g_clk~out0 filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178 } { 0.000ns 0.000ns 3.685ns } { 0.000ns 0.999ns 0.639ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "filter_shift:shift_reg\|shifter_ff\[1\]\[10\] xin\[10\] g_clk 4.695 ns register " "Info: tsu for register \"filter_shift:shift_reg\|shifter_ff\[1\]\[10\]\" (data pin = \"xin\[10\]\", clock pin = \"g_clk\") is 4.695 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.739 ns + Longest pin register " "Info: + Longest pin to register delay is 9.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.312 ns) 1.312 ns xin\[10\] 1 PIN PIN_AK18 1 " "Info: 1: + IC(0.000 ns) + CELL(1.312 ns) = 1.312 ns; Loc. = PIN_AK18; Fanout = 1; PIN Node = 'xin\[10\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { xin[10] } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 27 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.324 ns) + CELL(0.103 ns) 9.739 ns filter_shift:shift_reg\|shifter_ff\[1\]\[10\] 2 REG LC_X70_Y47_N3 2 " "Info: 2: + IC(8.324 ns) + CELL(0.103 ns) = 9.739 ns; Loc. = LC_X70_Y47_N3; Fanout = 2; REG Node = 'filter_shift:shift_reg\|shifter_ff\[1\]\[10\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.427 ns" { xin[10] filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.415 ns ( 14.53 % ) " "Info: Total cell delay = 1.415 ns ( 14.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.324 ns ( 85.47 % ) " "Info: Total interconnect delay = 8.324 ns ( 85.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.739 ns" { xin[10] filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.739 ns" { xin[10] xin[10]~out0 filter_shift:shift_reg|shifter_ff[1][10] } { 0.000ns 0.000ns 8.324ns } { 0.000ns 1.312ns 0.103ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.011 ns + " "Info: + Micro setup delay of destination is 0.011 ns" {  } { { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "g_clk destination 5.055 ns - Shortest register " "Info: - Shortest clock path from clock \"g_clk\" to destination register is 5.055 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns g_clk 1 CLK PIN_AA35 3774 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AA35; Fanout = 3774; CLK Node = 'g_clk'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { g_clk } "NODE_NAME" } } { "filter.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter.tdf" 24 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.412 ns) + CELL(0.644 ns) 5.055 ns filter_shift:shift_reg\|shifter_ff\[1\]\[10\] 2 REG LC_X70_Y47_N3 2 " "Info: 2: + IC(3.412 ns) + CELL(0.644 ns) = 5.055 ns; Loc. = LC_X70_Y47_N3; Fanout = 2; REG Node = 'filter_shift:shift_reg\|shifter_ff\[1\]\[10\]'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.056 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "filter_shift.tdf" "" { Text "F:/liu/我的硕士论文/w_fir/Quartus/filter_shift.tdf" 16 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 32.50 % ) " "Info: Total cell delay = 1.643 ns ( 32.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.412 ns ( 67.50 % ) " "Info: Total interconnect delay = 3.412 ns ( 67.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.055 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.055 ns" { g_clk g_clk~out0 filter_shift:shift_reg|shifter_ff[1][10] } { 0.000ns 0.000ns 3.412ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "9.739 ns" { xin[10] filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "9.739 ns" { xin[10] xin[10]~out0 filter_shift:shift_reg|shifter_ff[1][10] } { 0.000ns 0.000ns 8.324ns } { 0.000ns 1.312ns 0.103ns } "" } } { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.055 ns" { g_clk filter_shift:shift_reg|shifter_ff[1][10] } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.055 ns" { g_clk g_clk~out0 filter_shift:shift_reg|shifter_ff[1][10] } { 0.000ns 0.000ns 3.412ns } { 0.000ns 0.999ns 0.644ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}