filter.fit.eqn

matlab在fpga中的应用的三个具体事例

H1_rdaddress_buffer[1][0]_qfbk = H1_rdaddress_buffer[1][0];
K1L41 = !H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0]_qfbk & H1_ram_block[5][1] # !H1_rdaddress_buffer[1][0]_qfbk & H1_ram_block[4][1]);

--H1_rdaddress_buffer[1][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][0] at LC_X29_Y31_N9
--operation mode is normal

H1_rdaddress_buffer[1][0]_sload_eqn = H1_rdaddress_buffer[0][0];
H1_rdaddress_buffer[1][0] = DFFEA(H1_rdaddress_buffer[1][0]_sload_eqn, GLOBAL(g_clk), VCC, , , , );


--H1_ram_block[7][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][1] at M4K_X15_Y31
H1_ram_block[7][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][1]_PORT_A_address_reg = DFFE(H1_ram_block[7][1]_PORT_A_address, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[7][1]_clock_enable_0 = VCC;
H1_ram_block[7][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][1]_PORT_A_address_reg, , , , , , H1_ram_block[7][1]_clock_0, , H1_ram_block[7][1]_clock_enable_0, , , );
H1_ram_block[7][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][1]_PORT_A_data_out, H1_ram_block[7][1]_clock_0, , , H1_ram_block[7][1]_clock_enable_0);
H1_ram_block[7][1] = H1_ram_block[7][1]_PORT_A_data_out_reg[0];


--H1_ram_block[6][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][1] at M4K_X15_Y34
H1_ram_block[6][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][1]_PORT_A_address_reg = DFFE(H1_ram_block[6][1]_PORT_A_address, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[6][1]_clock_enable_0 = VCC;
H1_ram_block[6][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][1]_PORT_A_address_reg, , , , , , H1_ram_block[6][1]_clock_0, , H1_ram_block[6][1]_clock_enable_0, , , );
H1_ram_block[6][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][1]_PORT_A_data_out, H1_ram_block[6][1]_clock_0, , , H1_ram_block[6][1]_clock_enable_0);
H1_ram_block[6][1] = H1_ram_block[6][1]_PORT_A_data_out_reg[0];


--K1L51 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~259 at LC_X29_Y31_N5
--operation mode is normal

K1L51 = H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0] & H1_ram_block[7][1] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][1]);


--K1L61 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~263 at LC_X29_Y31_N6
--operation mode is normal

H1_rdaddress_buffer[1][3]_qfbk = H1_rdaddress_buffer[1][3];
K1L61 = H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][3]_qfbk & (K1L41 # K1L51);

--H1_rdaddress_buffer[1][3] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][3] at LC_X29_Y31_N6
--operation mode is normal

H1_rdaddress_buffer[1][3]_sload_eqn = H1_rdaddress_buffer[0][3];
H1_rdaddress_buffer[1][3] = DFFEA(H1_rdaddress_buffer[1][3]_sload_eqn, GLOBAL(g_clk), VCC, , , , );


--K1L591 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~508 at LC_X29_Y31_N0
--operation mode is normal

H1_rdaddress_buffer[1][1]_qfbk = H1_rdaddress_buffer[1][1];
K1L591 = !H1_rdaddress_buffer[1][0] & H1_rdaddress_buffer[1][1]_qfbk & !H1_rdaddress_buffer[1][2];

--H1_rdaddress_buffer[1][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][1] at LC_X29_Y31_N0
--operation mode is normal

H1_rdaddress_buffer[1][1]_sload_eqn = H1_rdaddress_buffer[0][1];
H1_rdaddress_buffer[1][1] = DFFEA(H1_rdaddress_buffer[1][1]_sload_eqn, GLOBAL(g_clk), VCC, , , , );


--H1_ram_block[10][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][1] at M4K_X51_Y58
H1_ram_block[10][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][1]_PORT_A_address_reg = DFFE(H1_ram_block[10][1]_PORT_A_address, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[10][1]_clock_enable_0 = VCC;
H1_ram_block[10][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][1]_PORT_A_address_reg, , , , , , H1_ram_block[10][1]_clock_0, , H1_ram_block[10][1]_clock_enable_0, , , );
H1_ram_block[10][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][1]_PORT_A_data_out, H1_ram_block[10][1]_clock_0, , , H1_ram_block[10][1]_clock_enable_0);
H1_ram_block[10][1] = H1_ram_block[10][1]_PORT_A_data_out_reg[0];


--H1_ram_block[2][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][1] at M4K_X51_Y15
H1_ram_block[2][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][1]_PORT_A_address_reg = DFFE(H1_ram_block[2][1]_PORT_A_address, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[2][1]_clock_enable_0 = VCC;
H1_ram_block[2][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][1]_PORT_A_address_reg, , , , , , H1_ram_block[2][1]_clock_0, , H1_ram_block[2][1]_clock_enable_0, , , );
H1_ram_block[2][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][1]_PORT_A_data_out, H1_ram_block[2][1]_clock_0, , , H1_ram_block[2][1]_clock_enable_0);
H1_ram_block[2][1] = H1_ram_block[2][1]_PORT_A_data_out_reg[0];


--K1L12 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~410 at LC_X29_Y31_N4
--operation mode is normal

K1L12 = K1L591 & (H1_rdaddress_buffer[1][3] & H1_ram_block[10][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[2][1]);


--K1L291 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result2059w~505 at LC_X30_Y31_N3
--operation mode is normal

K1L291 = !H1_rdaddress_buffer[1][1] & H1_rdaddress_buffer[1][0] & !H1_rdaddress_buffer[1][2];


--H1_ram_block[9][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[9][1] at M4K_X51_Y35
H1_ram_block[9][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[9][1]_PORT_A_address_reg = DFFE(H1_ram_block[9][1]_PORT_A_address, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[9][1]_clock_enable_0 = VCC;
H1_ram_block[9][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[9][1]_PORT_A_address_reg, , , , , , H1_ram_block[9][1]_clock_0, , H1_ram_block[9][1]_clock_enable_0, , , );
H1_ram_block[9][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[9][1]_PORT_A_data_out, H1_ram_block[9][1]_clock_0, , , H1_ram_block[9][1]_clock_enable_0);
H1_ram_block[9][1] = H1_ram_block[9][1]_PORT_A_data_out_reg[0];


--H1_ram_block[1][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][1] at M4K_X15_Y35
H1_ram_block[1][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][1]_PORT_A_address_reg = DFFE(H1_ram_block[1][1]_PORT_A_address, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1]_clock_0 = GLOBAL(g_clk);
H1_ram_block[1][1]_clock_enable_0 = VCC;
H1_ram_block[1][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][1]_PORT_A_address_reg, , , , , , H1_ram_block[1][1]_clock_0, , H1_ram_block[1][1]_clock_enable_0, , , );
H1_ram_block[1][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][1]_PORT_A_data_out, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1] = H1_ram_block[1][1]_PORT_A_data_out_reg[0];


--K1L71 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~373 at LC_X29_Y35_N0
--operation mode is normal

K1L71 = H1_rdaddress_buffer[1][3] & H1_ram_block[9][1] # !H1_rdaddress_buffer[1][3] & H1_ram_block[1][1];


--K1L52 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~553 at LC_X29_Y31_N7
--operation mode is normal

K1L52 = K1L61 # K1L12 # K1L291 & K1L71;


--K1L42 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~548 at LC_X29_Y31_N8
--operation mode is normal

K1L42 = K1L32 # K1L22 # K1L02 # K1L52;


--H1_ram_block[11][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][2] at M4K_X73_Y2
H1_ram_block[11][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][2]_PORT_A_address_reg = DFFE(H1_ram_block[11][2]_PORT_A_address, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[11][2]_clock_enable_0 = VCC;
H1_ram_block[11][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][2]_PORT_A_address_reg, , , , , , H1_ram_block[11][2]_clock_0, , H1_ram_block[11][2]_clock_enable_0, , , );
H1_ram_block[11][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][2]_PORT_A_data_out, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2] = H1_ram_block[11][2]_PORT_A_data_out_reg[0];


--H1_ram_block[3][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][2] at M4K_X109_Y31
H1_ram_block[3][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][2]_PORT_A_address_reg = DFFE(H1_ram_block[3][2]_PORT_A_address, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[3][2]_clock_enable_0 = VCC;
H1_ram_block[3][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][2]_PORT_A_address_reg, , , , , , H1_ram_block[3][2]_clock_0, , H1_ram_block[3][2]_clock_enable_0, , , );
H1_ram_block[3][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][2]_PORT_A_data_out, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2] = H1_ram_block[3][2]_PORT_A_data_out_reg[0];


--K1L53 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~412 at LC_X30_Y31_N9
--operation mode is normal

K1L53 = K1L491 & (H1_rdaddress_buffer[1][3] & H1_ram_block[11][2] # !H1_rdaddress_buffer[1][3] & H1_ram_block[3][2]);


--H1_ram_block[8][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][2] at M4K_X73_Y55
H1_ram_block[8][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][2]_PORT_A_address_reg = DFFE(H1_ram_block[8][2]_PORT_A_address, H1_ram_block[8][2]_clock_0, , , H1_ram_block[8][2]_clock_enable_0);
H1_ram_block[8][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[8][2]_clock_enable_0 = VCC;
H1_ram_block[8][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][2]_PORT_A_address_reg, , , , , , H1_ram_block[8][2]_clock_0, , H1_ram_block[8][2]_clock_enable_0, , , );
H1_ram_block[8][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][2]_PORT_A_data_out, H1_ram_block[8][2]_clock_0, , , H1_ram_block[8][2]_clock_enable_0);
H1_ram_block[8][2] = H1_ram_block[8][2]_PORT_A_data_out_reg[0];


--H1_ram_block[0][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][2] at M4K_X109_Y44
H1_ram_block[0][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][2]_PORT_A_address_reg = DFFE(H1_ram_block[0][2]_PORT_A_address, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[0][2]_clock_enable_0 = VCC;
H1_ram_block[0][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][2]_PORT_A_address_reg, , , , , , H1_ram_block[0][2]_clock_0, , H1_ram_block[0][2]_clock_enable_0, , , );
H1_ram_block[0][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][2]_PORT_A_data_out, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2] = H1_ram_block[0][2]_PORT_A_data_out_reg[0];


--K1L43 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~411 at LC_X31_Y31_N2
--operation mode is normal

K1L43 = K1L391 & (H1_rdaddress_buffer[1][3] & H1_ram_block[8][2] # !H1_rdaddress_buffer[1][3] & H1_ram_block[0][2]);


--H1_ram_block[14][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][2] at M4K_X51_Y67
H1_ram_block[14][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][2]_PORT_A_address_reg = DFFE(H1_ram_block[14][2]_PORT_A_address, H1_ram_block[14][2]_clock_0, , , H1_ram_block[14][2]_clock_enable_0);
H1_ram_block[14][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[14][2]_clock_enable_0 = VCC;
H1_ram_block[14][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][2]_PORT_A_address_reg, , , , , , H1_ram_block[14][2]_clock_0, , H1_ram_block[14][2]_clock_enable_0, , , );
H1_ram_block[14][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][2]_PORT_A_data_out, H1_ram_block[14][2]_clock_0, , , H1_ram_block[14][2]_clock_enable_0);
H1_ram_block[14][2] = H1_ram_block[14][2]_PORT_A_data_out_reg[0];


--H1_ram_block[12][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][2] at M4K_X51_Y24
H1_ram_block[12][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][2]_PORT_A_address_reg = DFFE(H1_ram_block[12][2]_PORT_A_address, H1_ram_block[12][2]_clock_0, , , H1_ram_block[12][2]_clock_enable_0);
H1_ram_block[12][2]_clock_0 = GLOBAL(g_clk);
H1_ram_block[12][2]_clock_enable_0 = VCC;
H1_ram_block[12][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][2]_PORT_A_address_reg, , , , , , H1_ram_block[12][2]_clock_0, , H1_ram_block[12][2]_clock_enable_0, , , );
H1_ram_block[12][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][2]_PORT_A_data_out, H1_ram_block[12][2]_clock_0, , , H1_ram_block[12][2]_clock_enable_0);
H1_ram_block[12][2] = H1_ram_block[12][2]_PORT_A_data_out_reg[0];


--K1L03 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~403 at LC_X31_Y31_N0
--operation mode is normal

K1L03 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[14][2] # !H1_rdaddress_buffer[1][1] & H1_ram_block[12][2]);


--H1_ram_block[15][2] is filter_co