filter.fit.eqn

matlab在fpga中的应用的三个具体事例

--E1_flip[14] is accumulator:shift_add|flip[14] at LC_X22_Y30_N2
--operation mode is normal

E1_flip[14]_lut_out = E1_accum[14];
E1_flip[14] = DFFEA(E1_flip[14]_lut_out, GLOBAL(g_clk), GLOBAL(clr), , B1_shift[18], , );


--E1_flip[15] is accumulator:shift_add|flip[15] at LC_X22_Y30_N3
--operation mode is normal

E1_flip[15]_sload_eqn = E1_accum[15];
E1_flip[15] = DFFEA(E1_flip[15]_sload_eqn, GLOBAL(g_clk), GLOBAL(clr), , B1_shift[18], , );


--E1_flip[16] is accumulator:shift_add|flip[16] at LC_X22_Y30_N6
--operation mode is normal

E1_flip[16]_sload_eqn = E1_accum[16];
E1_flip[16] = DFFEA(E1_flip[16]_sload_eqn, GLOBAL(g_clk), GLOBAL(clr), , B1_shift[18], , );


--E1_flip[17] is accumulator:shift_add|flip[17] at LC_X22_Y30_N8
--operation mode is normal

E1_flip[17]_sload_eqn = E1_accum[17];
E1_flip[17] = DFFEA(E1_flip[17]_sload_eqn, GLOBAL(g_clk), GLOBAL(clr), , B1_shift[18], , );


--E1_flip[18] is accumulator:shift_add|flip[18] at LC_X23_Y30_N8
--operation mode is normal

E1_flip[18]_lut_out = E1_accum[18];
E1_flip[18] = DFFEA(E1_flip[18]_lut_out, GLOBAL(g_clk), GLOBAL(clr), , B1_shift[18], , );


--H1_ram_block[7][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][0] at M4K_X51_Y34
H1_ram_block[7][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][0]_PORT_A_address_reg = DFFE(H1_ram_block[7][0]_PORT_A_address, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[7][0]_clock_enable_0 = VCC;
H1_ram_block[7][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][0]_PORT_A_address_reg, , , , , , H1_ram_block[7][0]_clock_0, , H1_ram_block[7][0]_clock_enable_0, , , );
H1_ram_block[7][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][0]_PORT_A_data_out, H1_ram_block[7][0]_clock_0, , , H1_ram_block[7][0]_clock_enable_0);
H1_ram_block[7][0] = H1_ram_block[7][0]_PORT_A_data_out_reg[0];


--H1_ram_block[5][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][0] at M4K_X15_Y39
H1_ram_block[5][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][0]_PORT_A_address_reg = DFFE(H1_ram_block[5][0]_PORT_A_address, H1_ram_block[5][0]_clock_0, , , H1_ram_block[5][0]_clock_enable_0);
H1_ram_block[5][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[5][0]_clock_enable_0 = VCC;
H1_ram_block[5][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][0]_PORT_A_address_reg, , , , , , H1_ram_block[5][0]_clock_0, , H1_ram_block[5][0]_clock_enable_0, , , );
H1_ram_block[5][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][0]_PORT_A_data_out, H1_ram_block[5][0]_clock_0, , , H1_ram_block[5][0]_clock_enable_0);
H1_ram_block[5][0] = H1_ram_block[5][0]_PORT_A_data_out_reg[0];


--K1L4 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~262 at LC_X30_Y31_N5
--operation mode is normal

K1L4 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[7][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[5][0]);


--H1_ram_block[6][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][0] at M4K_X73_Y33
H1_ram_block[6][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][0]_PORT_A_address_reg = DFFE(H1_ram_block[6][0]_PORT_A_address, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[6][0]_clock_enable_0 = VCC;
H1_ram_block[6][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][0]_PORT_A_address_reg, , , , , , H1_ram_block[6][0]_clock_0, , H1_ram_block[6][0]_clock_enable_0, , , );
H1_ram_block[6][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][0]_PORT_A_data_out, H1_ram_block[6][0]_clock_0, , , H1_ram_block[6][0]_clock_enable_0);
H1_ram_block[6][0] = H1_ram_block[6][0]_PORT_A_data_out_reg[0];


--H1_ram_block[4][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][0] at M4K_X73_Y5
H1_ram_block[4][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][0]_PORT_A_address_reg = DFFE(H1_ram_block[4][0]_PORT_A_address, H1_ram_block[4][0]_clock_0, , , H1_ram_block[4][0]_clock_enable_0);
H1_ram_block[4][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[4][0]_clock_enable_0 = VCC;
H1_ram_block[4][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][0]_PORT_A_address_reg, , , , , , H1_ram_block[4][0]_clock_0, , H1_ram_block[4][0]_clock_enable_0, , , );
H1_ram_block[4][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][0]_PORT_A_data_out, H1_ram_block[4][0]_clock_0, , , H1_ram_block[4][0]_clock_enable_0);
H1_ram_block[4][0] = H1_ram_block[4][0]_PORT_A_data_out_reg[0];


--K1L5 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~263 at LC_X30_Y31_N1
--operation mode is normal

K1L5 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[6][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[4][0]);


--K1L6 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~267 at LC_X30_Y31_N2
--operation mode is normal

K1L6 = !H1_rdaddress_buffer[1][3] & H1_rdaddress_buffer[1][2] & (K1L4 # K1L5);


--H1_ram_block[15][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][0] at M4K_X73_Y42
H1_ram_block[15][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][0]_PORT_A_address_reg = DFFE(H1_ram_block[15][0]_PORT_A_address, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[15][0]_clock_enable_0 = VCC;
H1_ram_block[15][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][0]_PORT_A_address_reg, , , , , , H1_ram_block[15][0]_clock_0, , H1_ram_block[15][0]_clock_enable_0, , , );
H1_ram_block[15][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][0]_PORT_A_data_out, H1_ram_block[15][0]_clock_0, , , H1_ram_block[15][0]_clock_enable_0);
H1_ram_block[15][0] = H1_ram_block[15][0]_PORT_A_data_out_reg[0];


--H1_ram_block[13][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][0] at M4K_X15_Y79
H1_ram_block[13][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][0]_PORT_A_address_reg = DFFE(H1_ram_block[13][0]_PORT_A_address, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[13][0]_clock_enable_0 = VCC;
H1_ram_block[13][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][0]_PORT_A_address_reg, , , , , , H1_ram_block[13][0]_clock_0, , H1_ram_block[13][0]_clock_enable_0, , , );
H1_ram_block[13][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][0]_PORT_A_data_out, H1_ram_block[13][0]_clock_0, , , H1_ram_block[13][0]_clock_enable_0);
H1_ram_block[13][0] = H1_ram_block[13][0]_PORT_A_data_out_reg[0];


--K1L2 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~56 at LC_X23_Y31_N8
--operation mode is normal

K1L2 = H1_rdaddress_buffer[1][1] & H1_ram_block[15][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[13][0];


--H1_ram_block[14][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][0] at M4K_X15_Y2
H1_ram_block[14][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][0]_PORT_A_address_reg = DFFE(H1_ram_block[14][0]_PORT_A_address, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[14][0]_clock_enable_0 = VCC;
H1_ram_block[14][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][0]_PORT_A_address_reg, , , , , , H1_ram_block[14][0]_clock_0, , H1_ram_block[14][0]_clock_enable_0, , , );
H1_ram_block[14][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][0]_PORT_A_data_out, H1_ram_block[14][0]_clock_0, , , H1_ram_block[14][0]_clock_enable_0);
H1_ram_block[14][0] = H1_ram_block[14][0]_PORT_A_data_out_reg[0];


--H1_ram_block[12][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][0] at M4K_X51_Y79
H1_ram_block[12][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][0]_PORT_A_address_reg = DFFE(H1_ram_block[12][0]_PORT_A_address, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[12][0]_clock_enable_0 = VCC;
H1_ram_block[12][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][0]_PORT_A_address_reg, , , , , , H1_ram_block[12][0]_clock_0, , H1_ram_block[12][0]_clock_enable_0, , , );
H1_ram_block[12][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][0]_PORT_A_data_out, H1_ram_block[12][0]_clock_0, , , H1_ram_block[12][0]_clock_enable_0);
H1_ram_block[12][0] = H1_ram_block[12][0]_PORT_A_data_out_reg[0];


--K1L3 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~61 at LC_X23_Y31_N1
--operation mode is normal

K1L3 = H1_rdaddress_buffer[1][1] & H1_ram_block[14][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[12][0];


--K1L7 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result44w~528 at LC_X23_Y31_N0
--operation mode is normal

K1L7 = H1_rdaddress_buffer[1][0] & K1L2 # !H1_rdaddress_buffer[1][0] & K1L3 # !H1_rdaddress_buffer[1][2];


--H1_ram_block[3][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][0] at M4K_X73_Y63
H1_ram_block[3][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][0]_PORT_A_address_reg = DFFE(H1_ram_block[3][0]_PORT_A_address, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[3][0]_clock_enable_0 = VCC;
H1_ram_block[3][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][0]_PORT_A_address_reg, , , , , , H1_ram_block[3][0]_clock_0, , H1_ram_block[3][0]_clock_enable_0, , , );
H1_ram_block[3][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][0]_PORT_A_data_out, H1_ram_block[3][0]_clock_0, , , H1_ram_block[3][0]_clock_enable_0);
H1_ram_block[3][0] = H1_ram_block[3][0]_PORT_A_data_out_reg[0];


--H1_ram_block[1][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][0] at M4K_X73_Y71
H1_ram_block[1][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][0]_PORT_A_address_reg = DFFE(H1_ram_block[1][0]_PORT_A_address, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[1][0]_clock_enable_0 = VCC;
H1_ram_block[1][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][0]_PORT_A_address_reg, , , , , , H1_ram_block[1][0]_clock_0, , H1_ram_block[1][0]_clock_enable_0, , , );
H1_ram_block[1][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][0]_PORT_A_data_out, H1_ram_block[1][0]_clock_0, , , H1_ram_block[1][0]_clock_enable_0);
H1_ram_block[1][0] = H1_ram_block[1][0]_PORT_A_data_out_reg[0];


--K1L8 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~96 at LC_X23_Y31_N5
--operation mode is normal

K1L8 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[3][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[1][0]);


--H1_ram_block[2][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][0] at M4K_X15_Y63
H1_ram_block[2][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][0]_PORT_A_address_reg = DFFE(H1_ram_block[2][0]_PORT_A_address, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[2][0]_clock_enable_0 = VCC;
H1_ram_block[2][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[2][0]_PORT_A_address_reg, , , , , , H1_ram_block[2][0]_clock_0, , H1_ram_block[2][0]_clock_enable_0, , , );
H1_ram_block[2][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[2][0]_PORT_A_data_out, H1_ram_block[2][0]_clock_0, , , H1_ram_block[2][0]_clock_enable_0);
H1_ram_block[2][0] = H1_ram_block[2][0]_PORT_A_data_out_reg[0];


--H1_ram_block[0][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][0] at M4K_X51_Y55
H1_ram_block[0][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][0]_PORT_A_address_reg = DFFE(H1_ram_block[0][0]_PORT_A_address, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0]_clock_0 = GLOBAL(g_clk);
H1_ram_block[0][0]_clock_enable_0 = VCC;
H1_ram_block[0][0]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][0]_PORT_A_address_reg, , , , , , H1_ram_block[0][0]_clock_0, , H1_ram_block[0][0]_clock_enable_0, , , );
H1_ram_block[0][0]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][0]_PORT_A_data_out, H1_ram_block[0][0]_clock_0, , , H1_ram_block[0][0]_clock_enable_0);
H1_ram_block[0][0] = H1_ram_block[0][0]_PORT_A_data_out_reg[0];


--K1L9 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~97 at LC_X22_Y31_N0
--operation mode is normal

K1L9 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[2][0] # !H1_rdaddress_buffer[1][1] & H1_ram_block[0][0]);


--K1L21 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result130w~117 at LC_X23_Y31_N6
--operation mode is normal

K1L21 = !H1_rdaddress_buffer[1][3] & !H1_rdaddress_buffer[1][2] & (K1L9 # K1L8);


--H1_ram_block[10][0] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][0] at M4K_X15_Y52
H1_ram_block[10][0]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][0]_PORT_A_address_reg = DFFE(H1_ram_block[10][0]_PORT_A_address, H1_ram_block[10][0]_clock_0, , , H1_ram_block[10][0]_clock_enable_0);