filter.tan.rpt

matlab在fpga中的应用的三个具体事例

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1S80F1508C7      ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; g_clk           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'g_clk'                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                     ; To                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 101.03 MHz ( period = 9.898 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.314 ns                ;
; N/A                                     ; 101.65 MHz ( period = 9.838 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a232       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.341 ns                ;
; N/A                                     ; 102.22 MHz ( period = 9.783 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178       ; accumulator:shift_add|accum[11] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.154 ns                ;
; N/A                                     ; 102.23 MHz ( period = 9.782 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a136       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.207 ns                ;
; N/A                                     ; 102.54 MHz ( period = 9.752 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a146       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.513 ns                ;
; N/A                                     ; 102.83 MHz ( period = 9.725 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178       ; accumulator:shift_add|accum[7]  ; g_clk      ; g_clk    ; None                        ; None                      ; 9.096 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178       ; accumulator:shift_add|accum[15] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.070 ns                ;
; N/A                                     ; 103.19 MHz ( period = 9.691 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a178       ; accumulator:shift_add|accum[17] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.068 ns                ;
; N/A                                     ; 103.55 MHz ( period = 9.657 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|out_address_reg_a[1] ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.451 ns                ;
; N/A                                     ; 103.61 MHz ( period = 9.652 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a161       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.099 ns                ;
; N/A                                     ; 103.68 MHz ( period = 9.645 ns )                    ; filter_coef:rom_coef|altsyncram:altsyncram_component|altsyncram_v331:auto_generated|ram_block1a184       ; accumulator:shift_add|accum[16] ; g_clk      ; g_clk    ; None                        ; None                      ; 9.344 ns                ;