📄 filter.map.eqn

📁 matlab在fpga中的应用的三个具体事例
💻 EQN
📖 第 1 页 / 共 5 页
字号:
上一页 1 2 3 45
--H1_ram_block[1][1] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[1][1]
H1_ram_block[1][1]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[1][1]_PORT_A_address_reg = DFFE(H1_ram_block[1][1]_PORT_A_address, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1]_clock_0 = g_clk;
H1_ram_block[1][1]_clock_enable_0 = VCC;
H1_ram_block[1][1]_PORT_A_data_out = MEMORY(, , H1_ram_block[1][1]_PORT_A_address_reg, , , , , , H1_ram_block[1][1]_clock_0, , H1_ram_block[1][1]_clock_enable_0, , , );
H1_ram_block[1][1]_PORT_A_data_out_reg = DFFE(H1_ram_block[1][1]_PORT_A_data_out, H1_ram_block[1][1]_clock_0, , , H1_ram_block[1][1]_clock_enable_0);
H1_ram_block[1][1] = H1_ram_block[1][1]_PORT_A_data_out_reg[0];


--K1L71 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~373
--operation mode is normal

K1L71 = H1_ram_block[9][1] & (H1_ram_block[1][1] # H1_rdaddress_buffer[1][3]) # !H1_ram_block[9][1] & H1_ram_block[1][1] & !H1_rdaddress_buffer[1][3];


--K1L52 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~553
--operation mode is normal

K1L52 = K1L61 # K1L12 # K1L291 & K1L71;


--K1L42 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result183w~548
--operation mode is normal

K1L42 = K1L32 # K1L22 # K1L02 # K1L52;


--H1_ram_block[11][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[11][2]
H1_ram_block[11][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[11][2]_PORT_A_address_reg = DFFE(H1_ram_block[11][2]_PORT_A_address, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2]_clock_0 = g_clk;
H1_ram_block[11][2]_clock_enable_0 = VCC;
H1_ram_block[11][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[11][2]_PORT_A_address_reg, , , , , , H1_ram_block[11][2]_clock_0, , H1_ram_block[11][2]_clock_enable_0, , , );
H1_ram_block[11][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[11][2]_PORT_A_data_out, H1_ram_block[11][2]_clock_0, , , H1_ram_block[11][2]_clock_enable_0);
H1_ram_block[11][2] = H1_ram_block[11][2]_PORT_A_data_out_reg[0];


--H1_ram_block[3][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[3][2]
H1_ram_block[3][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[3][2]_PORT_A_address_reg = DFFE(H1_ram_block[3][2]_PORT_A_address, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2]_clock_0 = g_clk;
H1_ram_block[3][2]_clock_enable_0 = VCC;
H1_ram_block[3][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[3][2]_PORT_A_address_reg, , , , , , H1_ram_block[3][2]_clock_0, , H1_ram_block[3][2]_clock_enable_0, , , );
H1_ram_block[3][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[3][2]_PORT_A_data_out, H1_ram_block[3][2]_clock_0, , , H1_ram_block[3][2]_clock_enable_0);
H1_ram_block[3][2] = H1_ram_block[3][2]_PORT_A_data_out_reg[0];


--K1L53 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~412
--operation mode is normal

K1L53 = K1L491 & (H1_rdaddress_buffer[1][3] & H1_ram_block[11][2] # !H1_rdaddress_buffer[1][3] & H1_ram_block[3][2]);


--H1_ram_block[8][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[8][2]
H1_ram_block[8][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[8][2]_PORT_A_address_reg = DFFE(H1_ram_block[8][2]_PORT_A_address, H1_ram_block[8][2]_clock_0, , , H1_ram_block[8][2]_clock_enable_0);
H1_ram_block[8][2]_clock_0 = g_clk;
H1_ram_block[8][2]_clock_enable_0 = VCC;
H1_ram_block[8][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[8][2]_PORT_A_address_reg, , , , , , H1_ram_block[8][2]_clock_0, , H1_ram_block[8][2]_clock_enable_0, , , );
H1_ram_block[8][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[8][2]_PORT_A_data_out, H1_ram_block[8][2]_clock_0, , , H1_ram_block[8][2]_clock_enable_0);
H1_ram_block[8][2] = H1_ram_block[8][2]_PORT_A_data_out_reg[0];


--H1_ram_block[0][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[0][2]
H1_ram_block[0][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[0][2]_PORT_A_address_reg = DFFE(H1_ram_block[0][2]_PORT_A_address, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2]_clock_0 = g_clk;
H1_ram_block[0][2]_clock_enable_0 = VCC;
H1_ram_block[0][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[0][2]_PORT_A_address_reg, , , , , , H1_ram_block[0][2]_clock_0, , H1_ram_block[0][2]_clock_enable_0, , , );
H1_ram_block[0][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[0][2]_PORT_A_data_out, H1_ram_block[0][2]_clock_0, , , H1_ram_block[0][2]_clock_enable_0);
H1_ram_block[0][2] = H1_ram_block[0][2]_PORT_A_data_out_reg[0];


--K1L43 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~411
--operation mode is normal

K1L43 = K1L391 & (H1_rdaddress_buffer[1][3] & H1_ram_block[8][2] # !H1_rdaddress_buffer[1][3] & H1_ram_block[0][2]);


--H1_ram_block[14][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[14][2]
H1_ram_block[14][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[14][2]_PORT_A_address_reg = DFFE(H1_ram_block[14][2]_PORT_A_address, H1_ram_block[14][2]_clock_0, , , H1_ram_block[14][2]_clock_enable_0);
H1_ram_block[14][2]_clock_0 = g_clk;
H1_ram_block[14][2]_clock_enable_0 = VCC;
H1_ram_block[14][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[14][2]_PORT_A_address_reg, , , , , , H1_ram_block[14][2]_clock_0, , H1_ram_block[14][2]_clock_enable_0, , , );
H1_ram_block[14][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[14][2]_PORT_A_data_out, H1_ram_block[14][2]_clock_0, , , H1_ram_block[14][2]_clock_enable_0);
H1_ram_block[14][2] = H1_ram_block[14][2]_PORT_A_data_out_reg[0];


--H1_ram_block[12][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[12][2]
H1_ram_block[12][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[12][2]_PORT_A_address_reg = DFFE(H1_ram_block[12][2]_PORT_A_address, H1_ram_block[12][2]_clock_0, , , H1_ram_block[12][2]_clock_enable_0);
H1_ram_block[12][2]_clock_0 = g_clk;
H1_ram_block[12][2]_clock_enable_0 = VCC;
H1_ram_block[12][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[12][2]_PORT_A_address_reg, , , , , , H1_ram_block[12][2]_clock_0, , H1_ram_block[12][2]_clock_enable_0, , , );
H1_ram_block[12][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[12][2]_PORT_A_data_out, H1_ram_block[12][2]_clock_0, , , H1_ram_block[12][2]_clock_enable_0);
H1_ram_block[12][2] = H1_ram_block[12][2]_PORT_A_data_out_reg[0];


--K1L03 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~403
--operation mode is normal

K1L03 = !H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[14][2] # !H1_rdaddress_buffer[1][1] & H1_ram_block[12][2]);


--H1_ram_block[15][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[15][2]
H1_ram_block[15][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[15][2]_PORT_A_address_reg = DFFE(H1_ram_block[15][2]_PORT_A_address, H1_ram_block[15][2]_clock_0, , , H1_ram_block[15][2]_clock_enable_0);
H1_ram_block[15][2]_clock_0 = g_clk;
H1_ram_block[15][2]_clock_enable_0 = VCC;
H1_ram_block[15][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[15][2]_PORT_A_address_reg, , , , , , H1_ram_block[15][2]_clock_0, , H1_ram_block[15][2]_clock_enable_0, , , );
H1_ram_block[15][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[15][2]_PORT_A_data_out, H1_ram_block[15][2]_clock_0, , , H1_ram_block[15][2]_clock_enable_0);
H1_ram_block[15][2] = H1_ram_block[15][2]_PORT_A_data_out_reg[0];


--H1_ram_block[13][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[13][2]
H1_ram_block[13][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[13][2]_PORT_A_address_reg = DFFE(H1_ram_block[13][2]_PORT_A_address, H1_ram_block[13][2]_clock_0, , , H1_ram_block[13][2]_clock_enable_0);
H1_ram_block[13][2]_clock_0 = g_clk;
H1_ram_block[13][2]_clock_enable_0 = VCC;
H1_ram_block[13][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[13][2]_PORT_A_address_reg, , , , , , H1_ram_block[13][2]_clock_0, , H1_ram_block[13][2]_clock_enable_0, , , );
H1_ram_block[13][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[13][2]_PORT_A_data_out, H1_ram_block[13][2]_clock_0, , , H1_ram_block[13][2]_clock_enable_0);
H1_ram_block[13][2] = H1_ram_block[13][2]_PORT_A_data_out_reg[0];


--K1L13 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~405
--operation mode is normal

K1L13 = H1_rdaddress_buffer[1][0] & (H1_rdaddress_buffer[1][1] & H1_ram_block[15][2] # !H1_rdaddress_buffer[1][1] & H1_ram_block[13][2]);


--K1L23 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~408
--operation mode is normal

K1L23 = H1_rdaddress_buffer[1][2] & H1_rdaddress_buffer[1][3] & (K1L03 # K1L13);


--H1_ram_block[5][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[5][2]
H1_ram_block[5][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[5][2]_PORT_A_address_reg = DFFE(H1_ram_block[5][2]_PORT_A_address, H1_ram_block[5][2]_clock_0, , , H1_ram_block[5][2]_clock_enable_0);
H1_ram_block[5][2]_clock_0 = g_clk;
H1_ram_block[5][2]_clock_enable_0 = VCC;
H1_ram_block[5][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[5][2]_PORT_A_address_reg, , , , , , H1_ram_block[5][2]_clock_0, , H1_ram_block[5][2]_clock_enable_0, , , );
H1_ram_block[5][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[5][2]_PORT_A_data_out, H1_ram_block[5][2]_clock_0, , , H1_ram_block[5][2]_clock_enable_0);
H1_ram_block[5][2] = H1_ram_block[5][2]_PORT_A_data_out_reg[0];


--H1_ram_block[4][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[4][2]
H1_ram_block[4][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[4][2]_PORT_A_address_reg = DFFE(H1_ram_block[4][2]_PORT_A_address, H1_ram_block[4][2]_clock_0, , , H1_ram_block[4][2]_clock_enable_0);
H1_ram_block[4][2]_clock_0 = g_clk;
H1_ram_block[4][2]_clock_enable_0 = VCC;
H1_ram_block[4][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[4][2]_PORT_A_address_reg, , , , , , H1_ram_block[4][2]_clock_0, , H1_ram_block[4][2]_clock_enable_0, , , );
H1_ram_block[4][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[4][2]_PORT_A_data_out, H1_ram_block[4][2]_clock_0, , , H1_ram_block[4][2]_clock_enable_0);
H1_ram_block[4][2] = H1_ram_block[4][2]_PORT_A_data_out_reg[0];


--K1L62 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~258
--operation mode is normal

K1L62 = !H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0] & H1_ram_block[5][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[4][2]);


--H1_ram_block[7][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[7][2]
H1_ram_block[7][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[7][2]_PORT_A_address_reg = DFFE(H1_ram_block[7][2]_PORT_A_address, H1_ram_block[7][2]_clock_0, , , H1_ram_block[7][2]_clock_enable_0);
H1_ram_block[7][2]_clock_0 = g_clk;
H1_ram_block[7][2]_clock_enable_0 = VCC;
H1_ram_block[7][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[7][2]_PORT_A_address_reg, , , , , , H1_ram_block[7][2]_clock_0, , H1_ram_block[7][2]_clock_enable_0, , , );
H1_ram_block[7][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[7][2]_PORT_A_data_out, H1_ram_block[7][2]_clock_0, , , H1_ram_block[7][2]_clock_enable_0);
H1_ram_block[7][2] = H1_ram_block[7][2]_PORT_A_data_out_reg[0];


--H1_ram_block[6][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[6][2]
H1_ram_block[6][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[6][2]_PORT_A_address_reg = DFFE(H1_ram_block[6][2]_PORT_A_address, H1_ram_block[6][2]_clock_0, , , H1_ram_block[6][2]_clock_enable_0);
H1_ram_block[6][2]_clock_0 = g_clk;
H1_ram_block[6][2]_clock_enable_0 = VCC;
H1_ram_block[6][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[6][2]_PORT_A_address_reg, , , , , , H1_ram_block[6][2]_clock_0, , H1_ram_block[6][2]_clock_enable_0, , , );
H1_ram_block[6][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[6][2]_PORT_A_data_out, H1_ram_block[6][2]_clock_0, , , H1_ram_block[6][2]_clock_enable_0);
H1_ram_block[6][2] = H1_ram_block[6][2]_PORT_A_data_out_reg[0];


--K1L72 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~259
--operation mode is normal

K1L72 = H1_rdaddress_buffer[1][1] & (H1_rdaddress_buffer[1][0] & H1_ram_block[7][2] # !H1_rdaddress_buffer[1][0] & H1_ram_block[6][2]);


--K1L82 is filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|mux_7dc:auto_generated|w_result317w~263
--operation mode is normal

K1L82 = H1_rdaddress_buffer[1][2] & !H1_rdaddress_buffer[1][3] & (K1L62 # K1L72);


--H1_ram_block[10][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[10][2]
H1_ram_block[10][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[10][2]_PORT_A_address_reg = DFFE(H1_ram_block[10][2]_PORT_A_address, H1_ram_block[10][2]_clock_0, , , H1_ram_block[10][2]_clock_enable_0);
H1_ram_block[10][2]_clock_0 = g_clk;
H1_ram_block[10][2]_clock_enable_0 = VCC;
H1_ram_block[10][2]_PORT_A_data_out = MEMORY(, , H1_ram_block[10][2]_PORT_A_address_reg, , , , , , H1_ram_block[10][2]_clock_0, , H1_ram_block[10][2]_clock_enable_0, , , );
H1_ram_block[10][2]_PORT_A_data_out_reg = DFFE(H1_ram_block[10][2]_PORT_A_data_out, H1_ram_block[10][2]_clock_0, , , H1_ram_block[10][2]_clock_enable_0);
H1_ram_block[10][2] = H1_ram_block[10][2]_PORT_A_data_out_reg[0];


--H1_ram_block[2][2] is filter_coef:rom_coef|altsyncram:altsyncram_component|ram_block[2][2]
H1_ram_block[2][2]_PORT_A_address = BUS(G2_reg[1], G3_reg[1], G4_reg[1], G5_reg[1], G6_reg[1], G7_reg[1], G8_reg[1], G9_reg[1], G01_reg[1], G11_reg[1], G21_reg[1], G31_reg[1]);
H1_ram_block[2][2]_PORT_A_address_reg = DFFE(H1_ram_block[2][2]_PORT_A_address, H1_ram_block[2][2]_clock_0, , , H1_ram_block[2][2]_clock_enable_0);
H1_ram_block[2][2]_clock_0 = g_clk;
H1_ram_block[2][2]_clock_enable_0 = VCC;
H1_ram_block[2][2]_PORT_A_data_out = MEMORY(, , H1_ram_block
上一页 1 2 3 45
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -