filter.csf.rpt

matlab在fpga中的应用的三个具体事例

| Preserve fewer node names                                | On                 |
| Optimize timing                                          | Normal Compilation |
| Optimize IOC register placement for timing               | On                 |
| Fast Fit compilation                                     | Off                |
| Perform WYSIWYG primitive resynthesis                    | Off                |
| Perform gate-level register retiming                     | Off                |
| Use Fitter timing information during synthesis           | Off                |
| Duplicate logic elements during fitting                  | Off                |
| Duplicate logic elements/resythesize LUTs during fitting | Off                |
| SignalProbe compilation                                  | Off                |
| Generate compressed bitstreams                           | Off                |
+----------------------------------------------------------+--------------------+

+-----------------------------------------------------------------------------+
| Messages                                                                    |
+-----------------------------------------------------------------------------+
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\filter_coef.tdf
  Info: Found entity 1: filter_coef
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\filter_shift.tdf
  Info: Found entity 1: filter_shift
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\p_s.tdf
  Info: Found entity 1: p_s
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\s_term.tdf
  Info: Found entity 1: s_term
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\accumulator.tdf
  Info: Found entity 1: accumulator
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\filter_con.tdf
  Info: Found entity 1: filter_con
Info: Found 1 design units and 1 entities in source file E:\w_fir\Quartus\filter.tdf
  Info: Found entity 1: filter
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\altsyncram.tdf
  Info: Found entity 1: altsyncram
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\lpm_mux.tdf
  Info: Found entity 1: lpm_mux
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\bypassff.tdf
  Info: Found entity 1: bypassff
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\altshift.tdf
  Info: Found entity 1: altshift
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\muxlut.tdf
  Info: Found entity 1: muxlut
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\lpm_add_sub.tdf
  Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file d:\quartus\libraries\megafunctions\alt_stratix_add_sub.tdf
  Info: Found entity 1: alt_stratix_add_sub
Info: Implemented 977 device resources
  Info: Implemented 15 input pins
  Info: Implemented 34 output pins
  Info: Implemented 672 logic cells
  Info: Implemented 256 RAM segments
Info: Selected device EP1S25F780C5 for design filter
Info: Annotating netlist with estimated timing delays
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node g_clk is an undefined clock
Info: Clock g_clk has Internal fmax of 35.17 MHz between source register filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][1] and destination register accumulator:shift_add|accum[18] (period= 28.431 ns)
  Info: + Longest register to register delay is 28.265 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; REG Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][1]'
    Info: 2: + IC(2.000 ns) + CELL(0.366 ns) = 2.366 ns; Loc. = Unassigned; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00014|result_node~1'
    Info: 3: + IC(1.040 ns) + CELL(0.280 ns) = 3.686 ns; Loc. = Unassigned; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~933'
    Info: 4: + IC(1.040 ns) + CELL(0.366 ns) = 5.092 ns; Loc. = Unassigned; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~928'
    Info: 5: + IC(1.040 ns) + CELL(0.366 ns) = 6.498 ns; Loc. = Unassigned; COMB Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|lpm_mux:rom_mux|muxlut:$00010|muxlut:$00020|result_node~35'
    Info: 6: + IC(1.080 ns) + CELL(0.610 ns) = 8.188 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[0]~COUT'
    Info: 7: + IC(1.040 ns) + CELL(0.098 ns) = 9.326 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[1]~COUT'
    Info: 8: + IC(1.040 ns) + CELL(0.098 ns) = 10.464 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[2]~COUT'
    Info: 9: + IC(1.040 ns) + CELL(0.098 ns) = 11.602 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[3]~COUT'
    Info: 10: + IC(1.040 ns) + CELL(0.098 ns) = 12.740 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[4]~COUT'
    Info: 11: + IC(1.040 ns) + CELL(0.098 ns) = 13.878 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[5]~COUT'
    Info: 12: + IC(1.040 ns) + CELL(0.098 ns) = 15.016 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[6]~COUT'
    Info: 13: + IC(1.040 ns) + CELL(0.098 ns) = 16.154 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[7]~COUT'
    Info: 14: + IC(1.040 ns) + CELL(0.098 ns) = 17.292 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[8]~COUT'
    Info: 15: + IC(1.040 ns) + CELL(0.098 ns) = 18.430 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[9]~COUT'
    Info: 16: + IC(1.040 ns) + CELL(0.098 ns) = 19.568 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[10]~COUT'
    Info: 17: + IC(1.040 ns) + CELL(0.098 ns) = 20.706 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[11]~COUT'
    Info: 18: + IC(1.040 ns) + CELL(0.098 ns) = 21.844 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[12]~COUT'
    Info: 19: + IC(1.040 ns) + CELL(0.098 ns) = 22.982 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[13]~COUT'
    Info: 20: + IC(1.040 ns) + CELL(0.098 ns) = 24.120 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[14]~COUT'
    Info: 21: + IC(1.040 ns) + CELL(0.098 ns) = 25.258 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|add_sub_cell[15]~COUT'
    Info: 22: + IC(1.040 ns) + CELL(0.469 ns) = 26.767 ns; Loc. = Unassigned; COMB Node = 'accumulator:shift_add|lpm_add_sub:adder|alt_stratix_add_sub:stratix_adder|result[16]'
    Info: 23: + IC(1.040 ns) + CELL(0.458 ns) = 28.265 ns; Loc. = Unassigned; REG Node = 'accumulator:shift_add|accum[18]'
    Info: Total cell delay = 4.385 ns
    Info: Total interconnect delay = 23.880 ns
  Info: - Smallest clock skew is 0.000 ns
    Info: + Shortest clock path from clock g_clk to destination register is 3.681 ns
      Info: 1: + IC(0.000 ns) + CELL(0.927 ns) = 0.927 ns; Loc. = Unassigned; CLK Node = 'g_clk'
      Info: 2: + IC(2.212 ns) + CELL(0.542 ns) = 3.681 ns; Loc. = Unassigned; REG Node = 'accumulator:shift_add|accum[18]'
      Info: Total cell delay = 1.469 ns
      Info: Total interconnect delay = 2.212 ns
    Info: - Longest clock path from clock g_clk to source register is 3.681 ns
      Info: 1: + IC(0.000 ns) + CELL(0.927 ns) = 0.927 ns; Loc. = Unassigned; CLK Node = 'g_clk'
      Info: 2: + IC(2.212 ns) + CELL(0.542 ns) = 3.681 ns; Loc. = Unassigned; REG Node = 'filter_coef:rom_coef|altsyncram:altsyncram_component|rdaddress_buffer[1][1]'
      Info: Total cell delay = 1.469 ns
      Info: Total interconnect delay = 2.212 ns
  Info: + Micro clock to output delay of source is 0.156 ns
  Info: + Micro setup delay of destination is 0.010 ns

+-----------------------------------------------------------------------------+
| Hierarchy                                                                   |
+-----------------------------------------------------------------------------+
Hierarchy
  filter
    filter_con:cont
    s_term:p_s_c
      p_s:regs
      p_s:regs[1]
      p_s:regs[2]
      p_s:regs[3]
      p_s:regs[4]
      p_s:regs[5]
      p_s:regs[6]
      p_s:regs[7]