generator.xrf

matlab在fpga中的应用的三个具体事例

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\program files\synplicity\synplify_73\lib\vhd\std.vhd, synplify
source_file = 2, d:\924lyj\924\generator_sin.vhd, synplify
source_file = 3, c:\program files\synplicity\synplify_73\lib\vhd\std1164.vhd, synplify
source_file = 4, c:\program files\synplicity\synplify_73\lib\vhd\arith.vhd, synplify
source_file = 5, c:\program files\synplicity\synplify_73\lib\vhd\unsigned.vhd, synplify
source_file = 6, d:\924lyj\924\generator_acc6.vhd, synplify
source_file = 7, d:\924lyj\924\generator_adder.vhd, synplify
source_file = 8, d:\924lyj\924\generator_and2.vhd, synplify
source_file = 9, d:\924lyj\924\generator_mux.vhd, synplify
source_file = 10, d:\924lyj\924\generator_reg6.vhd, synplify
source_file = 11, d:\924lyj\924\generator_reg8.vhd, synplify
source_file = 12, d:\924lyj\924\generator.vhd, synplify
design_name=generator
instance = port, DATA[5:0], , generator, 12, 32:2:32:5
instance = port, PR, , generator, 12, 33:2:33:3
instance = port, FR, , generator, 12, 34:2:34:3
instance = port, CLR, , generator, 12, 35:2:35:4
instance = port, CE, , generator, 12, 36:2:36:3
instance = port, Q[7:0], , generator, 12, 37:2:37:2
instance = port, CLK, , generator, 12, 38:2:38:4
instance = comp, CLK_in, , generator, 12, 38:2:38:4
instance = comp, Q_out_7_, , generator, 12, 37:2:37:2
instance = comp, Q_out_6_, , generator, 12, 37:2:37:2
instance = comp, Q_out_5_, , generator, 12, 37:2:37:2
instance = comp, Q_out_4_, , generator, 12, 37:2:37:2
instance = comp, Q_out_3_, , generator, 12, 37:2:37:2
instance = comp, Q_out_2_, , generator, 12, 37:2:37:2
instance = comp, Q_out_1_, , generator, 12, 37:2:37:2
instance = comp, Q_out_0_, , generator, 12, 37:2:37:2
instance = comp, CE_in, , generator, 12, 36:2:36:3
instance = comp, CLR_in, , generator, 12, 35:2:35:4
instance = comp, FR_in, , generator, 12, 34:2:34:3
instance = comp, PR_in, , generator, 12, 33:2:33:3
instance = comp, DATA_in_5_, , generator, 12, 32:2:32:5
instance = comp, DATA_in_4_, , generator, 12, 32:2:32:5
instance = comp, DATA_in_3_, , generator, 12, 32:2:32:5
instance = comp, DATA_in_2_, , generator, 12, 32:2:32:5
instance = comp, DATA_in_1_, , generator, 12, 32:2:32:5
instance = comp, DATA_in_0_, , generator, 12, 32:2:32:5
instance = comp, U1, , generator, 12, 109:0:109:1
instance = comp, U6, , generator, 12, 117:0:117:1
instance = comp, U2, , generator, 12, 125:0:125:1
instance = comp, U3, , generator, 12, 133:0:133:1
instance = comp, U4, , generator, 12, 139:0:139:1
instance = comp, U7, , generator, 12, 147:0:147:1
instance = comp, U8, , generator, 12, 155:0:155:1
instance = comp, U9, , generator, 12, 161:0:161:1
design_name=generator_and2_1
instance = comp, O_0_and2_0, , generator_and2_1, 8, 23:6:23:14
design_name=generator_and2
instance = comp, O_0_and2_0, , generator_and2, 8, 23:6:23:14
design_name=generator_reg8
instance = comp, Q_7_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_6_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_5_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_4_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_3_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_2_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_1_, , generator_reg8, 11, 34:2:34:3
instance = comp, Q_0_, , generator_reg8, 11, 34:2:34:3
design_name=generator_acc6
instance = comp, Q_5_, , generator_acc6, 6, 39:2:39:3
instance = comp, Q_4_, , generator_acc6, 6, 39:2:39:3
instance = comp, Q_3_, , generator_acc6, 6, 39:2:39:3
instance = comp, Q_2_, , generator_acc6, 6, 39:2:39:3
instance = comp, Q_1_, , generator_acc6, 6, 39:2:39:3
instance = comp, Q_0_, , generator_acc6, 6, 39:2:39:3
design_name=generator_adder
instance = comp, q_add5_0, , generator_adder, 7, 27:7:27:11
instance = comp, q_add4_0, , generator_adder, 7, 27:7:27:11
instance = comp, q_add3_0, , generator_adder, 7, 27:7:27:11
instance = comp, q_add2_0, , generator_adder, 7, 27:7:27:11
instance = comp, q_add1_0, , generator_adder, 7, 27:7:27:11
instance = comp, q_add0_0, , generator_adder, 7, 27:7:27:11
design_name=generator_reg6_1
design_name=generator_sin
instance = comp, q_39_17_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_17_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_28_0_a1_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_28_0_a1_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_34_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_34_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_48_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_48_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_52_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_52_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_84_a0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_84_a0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_101_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_101_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_107_a_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_40_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_40_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_72_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_72_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_23_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_23_0_a_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_56_0_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_59_0_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_62_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_64_0_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_95_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_98_0, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_32_0_Z, , generator_sin, 12, 117:0:117:1
instance = comp, q_39_44_0_Z, , generator_sin, 12, 117:0:117:1
design_name=generator_reg6
instance = comp, Q_5_, , generator_reg6, 10, 33:2:33:3
instance = comp, Q_4_, , generator_reg6, 10, 33:2:33:3
instance = comp, Q_3_, , generator_reg6, 10, 33:2:33:3
instance = comp, Q_2_, , generator_reg6, 10, 33:2:33:3
instance = comp, Q_1_, , generator_reg6, 10, 33:2:33:3
instance = comp, Q_0_, , generator_reg6, 10, 33:2:33:3