system_0.ptf

在linux下生成的zImage文件

               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
         PORT_WIRING 
         {
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_addr
            {
               Is_Enabled = "1";
               direction = "input";
               width = "12";
            }
            PORT zs_ba
            {
               Is_Enabled = "1";
               direction = "input";
               width = "2";
            }
            PORT zs_cas_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cke
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_cs_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_dq
            {
               Is_Enabled = "1";
               direction = "inout";
               width = "16";
            }
            PORT zs_dqm
            {
               Is_Enabled = "1";
               direction = "input";
               width = "2";
            }
            PORT zs_ras_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
            PORT zs_we_n
            {
               Is_Enabled = "1";
               direction = "input";
               width = "1";
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram_0.v, __PROJECT_DIRECTORY__/sdram_0_test_component.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE epcs_controller
   {
      class = "altera_avalon_epcs_flash_controller";
      class_version = "6.01";
      SLAVE epcs_control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Nonvolatile_Storage = "1";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Is_Memory_Device = "1";
            Address_Width = "9";
            Data_Width = "32";
            Has_IRQ = "1";
            Read_Wait_States = "1";
            Write_Wait_States = "1";
            MASTERED_BY cpu_0/instruction_master
            {
               priority = "1";
            }
            MASTERED_BY cpu_0/data_master
            {
               priority = "1";
            }
            IRQ_MASTER cpu_0/data_master
            {
               IRQ_Number = "0";
            }
            Base_Address = "0x00680800";
            Address_Group = "0";
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_epcs_flash_controller";
            flash_reference_designator = "U30";
         }
         PORT_WIRING 
         {
            PORT address
            {
               Is_Enabled = "1";
               direction = "input";
               type = "address";
               width = "9";
            }
            PORT chipselect
            {
               Is_Enabled = "1";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT data_from_cpu
            {
               Is_Enabled = "0";
               direction = "input";
               type = "writedata";
               width = "16";
            }
            PORT data_to_cpu
            {
               Is_Enabled = "0";
               direction = "output";
               type = "readdata";
               width = "16";
            }
            PORT dataavailable
            {
               Is_Enabled = "1";
               direction = "output";
               type = "dataavailable";
               width = "1";
            }
            PORT endofpacket
            {
               Is_Enabled = "1";
               direction = "output";
               type = "endofpacket";
               width = "1";
            }
            PORT epcs_select
            {
               Is_Enabled = "0";
               direction = "input";
               type = "chipselect";
               width = "1";
            }
            PORT irq
            {
               Is_Enabled = "1";
               direction = "output";
               type = "irq";
               width = "1";
            }
            PORT mem_addr
            {
               Is_Enabled = "0";
               direction = "input";
               type = "address";
               width = "3";
            }
            PORT read_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "read_n";
               width = "1";
            }
            PORT readdata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readdata";
               width = "32";
            }
            PORT readyfordata
            {
               Is_Enabled = "1";
               direction = "output";
               type = "readyfordata";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "reset_n";
               width = "1";
            }
            PORT write_n
            {
               Is_Enabled = "1";
               direction = "input";
               type = "write_n";
               width = "1";
            }
            PORT writedata
            {
               Is_Enabled = "1";
               direction = "input";
               type = "writedata";
               width = "32";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXII,STRATIXIIGX";
         Fixed_Module_Name = "epcs_controller";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         databits = "8";
         targetclock = "20";
         clockunits = "MHz";
         clockmult = "1000000";
         numslaves = "1";
         ismaster = "1";
         clockpolarity = "0";
         clockphase = "0";
         lsbfirst = "0";
         extradelay = "0";
         targetssdelay = "100";
         delayunits = "us";
         delaymult = "1e-006";
         prefix = "epcs_";
         register_offset = "0x200";
         MAKE 
         {
            MACRO 
            {
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
            }
            MASTER cpu_0
            {
               MACRO 
               {
                  BOOTS_FROM_EPCS = "0";
                  BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
                  CPU_CLASS = "altera_nios2";
                  CPU_RESET_ADDRESS = "0x0";
               }
            }
            TARGET delete_placeholder_warning
            {
               epcs_controller 
               {
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
                  Is_Phony = "1";
                  Target_File = "do_delete_placeholder_warning";
               }
            }
            TARGET flashfiles
            {
               epcs_controller 
               {
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash=U30 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi";
                  Dependency = "$(ELF)";
                  Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
               }
            }
            TARGET sim
            {
               epcs_controller 
               {
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
                  Command3 = "touch $(SIMDIR)/dummy_file";
                  Dependency = "$(ELF)";
                  Target_File = "$(SIMDIR)/dummy_file";
               }
            }
         }
         clockunit = "kHz";
         contents_info = "SIMDIR/epcs_controller_boot_rom.hex 1130817967 SIMDIR/epcs_controller_boot_rom.dat 1130817967 ";
         delayunit = "us";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.v";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
   }
   MODULE jtag_uart_0
   {
      class = "altera_avalon_jtag_uart";
      class_version = "6.01";
      iss_model_name = "altera_avalon_jtag_uart";
      SLAVE avalon_jtag_slave
      {
         SYSTEM_BUILDER_