📄 system_0.ptf
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direction = "inout";
type = "data";
}
PORT address
{
width = "22";
is_shared = "1";
direction = "input";
type = "address";
}
PORT read_n
{
width = "1";
is_shared = "1";
direction = "input";
type = "read_n";
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "U20";
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Nonvolatile_Storage = "1";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Base_Address = "0x00000000";
Data_Width = "8";
Address_Width = "22";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Write_Wait_States = "160ns";
Read_Wait_States = "160ns";
Setup_Time = "40ns";
Hold_Time = "40ns";
Address_Span = "4194304";
MASTERED_BY tri_state_bridge_0/tristate_master
{
priority = "1";
}
Is_Base_Locked = "1";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
}
SYSTEM_BUILDER_INFO
{
Make_Memory_Model = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "40";
Wait_Value = "160";
Hold_Value = "40";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "4194304";
MAKE
{
MACRO
{
CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_0_FLASHTARGET_TMP1:0=)";
CFI_FLASH_0_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
}
MASTER cpu_0
{
MACRO
{
BOOT_COPIER = "boot_loader_cfi.srec";
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
}
}
TARGET delete_placeholder_warning
{
cfi_flash_0
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET flashfiles
{
cfi_flash_0
{
Command1 = "@echo Post-processing to create $(notdir $@)";
Command2 = "elf2flash --input=$(ELF) --flash=U20 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x3FFFFF --reset=$(CPU_RESET_ADDRESS) ";
Dependency = "$(ELF)";
Target_File = "$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash";
}
}
TARGET sim
{
cfi_flash_0
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "SIMDIR/cfi_flash_0.dat 1130817963 ";
}
}
MODULE sdram_0
{
class = "altera_avalon_new_sdram_controller";
class_version = "6.01";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "16";
Simulation_Num_Lanes = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00800000";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
Address_Group = "0";
}
PORT_WIRING
{
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "16";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT az_addr
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "22";
}
PORT az_be_n
{
Is_Enabled = "1";
direction = "input";
type = "byteenable_n";
width = "2";
}
PORT az_cs
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT az_data
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
PORT az_rd_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT az_wr_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT za_data
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT za_valid
{
Is_Enabled = "1";
direction = "output";
type = "readdatavalid";
width = "1";
}
PORT za_waitrequest
{
Is_Enabled = "1";
direction = "output";
type = "waitrequest";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Disable_Simulation_Port_Wiring = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk_50";
View
{
Settings_Summary = "4194304 x 16<br>
Memory size: 8 MBytes<br>
64 MBits
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "1";
sdram_data_width = "16";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100";
cas_latency = "3";
t_rfc = "70";
t_rp = "20";
t_mrd = "3";
t_rcd = "20";
t_ac = "5.5";
t_wr = "14";
init_refresh_commands = "2";
init_nop_delay = "0";
shared_data = "0";
starvation_indicator = "0";
tristate_bridge_slave = "";
is_initialized = "1";
sdram_bank_width = "2";
MAKE
{
TARGET delete_placeholder_warning
{
sdram_0
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET sim
{
sdram_0
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "SIMDIR/sdram_0.dat 1130817965 ";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
radix = "hexadecimal";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL g
{
name = "clk";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL k
{
name = "za_cannotrefresh";
suppress = "1";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
SIGNAL m
{
name = "zs_addr";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL n
{
name = "zs_ba";
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