📄 negativesequencesource.mdl
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ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
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}
PropName "Components"
}
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PropName "Components"
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Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
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PropName "ConfigurationSets"
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Simulink.ConfigSet {
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$ObjectID 1
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Block {
BlockType BusCreator
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
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Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType ComplexToMagnitudeAngle
Output "Magnitude and angle"
SampleTime "-1"
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Block {
BlockType Constant
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Block {
BlockType DataTypeConversion
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
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ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
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Block {
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Block {
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Block {
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gainval "1.0"
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LowerSaturationLimit "-inf"
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RTWStateStorageClass "Auto"
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BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
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Block {
BlockType From
IconDisplay "Tag"
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Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
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RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
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Block {
BlockType Goto
IconDisplay "Tag"
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Block {
BlockType Ground
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Block {
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BusObject "BusObject"
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DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
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Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
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LogicDataType "uint(8)"
SampleTime "-1"
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Block {
BlockType Lookup
InputValues "[-4:5]"
OutputValues " rand(1,10)-0.5"
LookUpMeth "Interpolation-Extrapolation"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
LUTDesignTableMode "Redesign Table"
LUTDesignDataSource "Block Dialog"
LUTDesignFunctionName "sqrt(x)"
LUTDesignUseExistingBP on
LUTDesignRelError "0.01"
LUTDesignAbsError "1e-6"
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Block {
BlockType MultiPortSwitch
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zeroidx off
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OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
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SampleTime "-1"
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Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
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BusObject "BusObject"
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Block {
BlockType Outport
Port "1"
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BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
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Block {
BlockType PMComponent
SubClassName "unknown"
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Block {
BlockType PMIOPort
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Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType RealImagToComplex
Input "Real and imag"
ConstantPart "0"
SampleTime "-1"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
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LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
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Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
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Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
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IndexIsStartValue off
OutputPortSize "1"
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Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
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Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
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Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType Trigonometry
Operator "sin"
OutputSignalType "auto"
SampleTime "-1"
}
Block {
BlockType UnitDelay
X0 "0"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
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AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
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FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "negativeSequenceSource"
Location [5, 82, 1002, 806]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "3-Phase \nProgrammable \nVoltage Source"
Ports [0, 0, 0, 0, 0, 1, 3]
Position [205, 154, 265, 206]
SourceBlock "powerlib/Electrical\nSources/Three-Phase\nProgr"
"ammable\nVoltage Source"
SourceType "Three-Phase Programmable Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PositiveSequence "[1000 -30 50]"
VariationEntity "Amplitude"
VariationType "Step"
VariationStep "0.5"
VariationRate "10"
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