hubio.h

上传linux-jx2410的源代码

	struct	{
		bdrkreg_t	i_rsvd			  :	22;
		bdrkreg_t	i_maxbrst		  :	10;
		bdrkreg_t	i_rsvd_1		  :	 4;
		bdrkreg_t	i_d_avail_sel		  :	 2;
		bdrkreg_t	i_maxrtry		  :	10;
		bdrkreg_t	i_rsvd_2		  :	 1;
		bdrkreg_t	i_remote_power		  :	 1;
		bdrkreg_t	i_llp_stat		  :	 2;
		bdrkreg_t	i_bm8			  :	 1;
		bdrkreg_t	i_llp_en		  :	 1;
		bdrkreg_t	i_rsvd_3		  :	 1;
		bdrkreg_t	i_wrmrst		  :	 1;
		bdrkreg_t	i_rsvd_4		  :	 2;
		bdrkreg_t	i_nullto		  :	 6;
	} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This is simply a status registers that monitors the LLP error       *
 * rate.                                                                *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_illr_u {
	bdrkreg_t	ii_illr_regval;
	struct	{
		bdrkreg_t	i_sn_cnt		  :	16;
		bdrkreg_t	i_cb_cnt		  :	16;
		bdrkreg_t	i_rsvd			  :	32;
	} ii_illr_fld_s;
} ii_illr_u_t;

#else

typedef union ii_illr_u {
	bdrkreg_t	ii_illr_regval;
	struct  {
		bdrkreg_t	i_rsvd                    :	32;
		bdrkreg_t	i_cb_cnt                  :	16;
		bdrkreg_t	i_sn_cnt                  :	16;
	} ii_illr_fld_s;
} ii_illr_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  All II-detected non-BTE error interrupts are           *
 * specified via this register.                                         *
 * NOTE: The PI interrupt register address is hardcoded in the II. If   *
 * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
 * packet) to address offset 0x0180_0090 within the local register      *
 * address space of PI0 on the node specified by the NODE field. If     *
 * PI_ID==1, then the II sends the interrupt request to address         *
 * offset 0x01A0_0090 within the local register address space of PI1    *
 * on the node specified by the NODE field.                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_iidsr_u {
	bdrkreg_t	ii_iidsr_regval;
	struct  {
		bdrkreg_t	i_level                   :	 7;
		bdrkreg_t	i_rsvd_4		  :	 1;
		bdrkreg_t       i_pi_id                   :      1;
		bdrkreg_t	i_node			  :	 8;
		bdrkreg_t       i_rsvd_3                  :      7;
		bdrkreg_t	i_enable		  :	 1;
		bdrkreg_t	i_rsvd_2		  :	 3;
		bdrkreg_t	i_int_sent		  :	 1;
		bdrkreg_t       i_rsvd_1                  :      3;
		bdrkreg_t	i_pi0_forward_int	  :	 1;
		bdrkreg_t	i_pi1_forward_int	  :	 1;
		bdrkreg_t	i_rsvd			  :	30;
	} ii_iidsr_fld_s;
} ii_iidsr_u_t;

#else

typedef union ii_iidsr_u {
	bdrkreg_t	ii_iidsr_regval;
	struct	{
		bdrkreg_t	i_rsvd			  :	30;
		bdrkreg_t	i_pi1_forward_int	  :	 1;
		bdrkreg_t	i_pi0_forward_int	  :	 1;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_int_sent		  :	 1;
		bdrkreg_t	i_rsvd_2		  :	 3;
		bdrkreg_t	i_enable		  :	 1;
		bdrkreg_t	i_rsvd_3		  :	 7;
		bdrkreg_t	i_node			  :	 8;
		bdrkreg_t	i_pi_id			  :	 1;
		bdrkreg_t	i_rsvd_4		  :	 1;
		bdrkreg_t	i_level			  :	 7;
	} ii_iidsr_fld_s;
} ii_iidsr_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There are two instances of this register. This register is used     *
 * for matching up the incoming responses from the graphics widget to   *
 * the processor that initiated the graphics operation. The             *
 * write-responses are converted to graphics credits and returned to    *
 * the processor so that the processor interface can manage the flow    *
 * control.                                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_igfx0_u {
	bdrkreg_t	ii_igfx0_regval;
	struct	{
		bdrkreg_t	i_w_num			  :	 4;
		bdrkreg_t       i_pi_id                   :      1;
		bdrkreg_t	i_n_num			  :	 8;
		bdrkreg_t       i_rsvd_1                  :      3;
		bdrkreg_t       i_p_num                   :      1;
		bdrkreg_t       i_rsvd                    :     47;
	} ii_igfx0_fld_s;
} ii_igfx0_u_t;

#else

typedef union ii_igfx0_u {
	bdrkreg_t	ii_igfx0_regval;
	struct  {
		bdrkreg_t	i_rsvd                    :	47;
		bdrkreg_t	i_p_num                   :	 1;
		bdrkreg_t	i_rsvd_1                  :	 3;
		bdrkreg_t	i_n_num                   :	 8;
		bdrkreg_t	i_pi_id                   :	 1;
		bdrkreg_t	i_w_num                   :	 4;
	} ii_igfx0_fld_s;
} ii_igfx0_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There are two instances of this register. This register is used     *
 * for matching up the incoming responses from the graphics widget to   *
 * the processor that initiated the graphics operation. The             *
 * write-responses are converted to graphics credits and returned to    *
 * the processor so that the processor interface can manage the flow    *
 * control.                                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_igfx1_u {
	bdrkreg_t	ii_igfx1_regval;
	struct  {
		bdrkreg_t	i_w_num                   :	 4;
		bdrkreg_t	i_pi_id			  :	 1;
		bdrkreg_t	i_n_num			  :	 8;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_p_num			  :	 1;
		bdrkreg_t	i_rsvd			  :	47;
	} ii_igfx1_fld_s;
} ii_igfx1_u_t;

#else

typedef union ii_igfx1_u {
	bdrkreg_t	ii_igfx1_regval;
	struct	{
		bdrkreg_t	i_rsvd			  :	47;
		bdrkreg_t	i_p_num			  :	 1;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_n_num			  :	 8;
		bdrkreg_t	i_pi_id			  :	 1;
		bdrkreg_t	i_w_num			  :	 4;
	} ii_igfx1_fld_s;
} ii_igfx1_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There are two instances of this registers. These registers are      *
 * used as scratch registers for software use.                          *
 *                                                                      *
 ************************************************************************/




typedef union ii_iscr0_u {
	bdrkreg_t	ii_iscr0_regval;
	struct  {
		bdrkreg_t	i_scratch                 :	64;
	} ii_iscr0_fld_s;
} ii_iscr0_u_t;




/************************************************************************
 *                                                                      *
 *  There are two instances of this registers. These registers are      *
 * used as scratch registers for software use.                          *
 *                                                                      *
 ************************************************************************/




typedef union ii_iscr1_u {
	bdrkreg_t	ii_iscr1_regval;
	struct  {
		bdrkreg_t	i_scratch                 :	64;
	} ii_iscr1_fld_s;
} ii_iscr1_u_t;




/************************************************************************
 *                                                                      *
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Bedrock Big Window to a 48-bit       *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the Bedrock is thus the lower         *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_itte1_u {
	bdrkreg_t	ii_itte1_regval;
	struct  {
		bdrkreg_t	i_offset                  :	 5;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_w_num			  :	 4;
		bdrkreg_t	i_iosp			  :	 1;
		bdrkreg_t	i_rsvd			  :	51;
	} ii_itte1_fld_s;
} ii_itte1_u_t;

#else

typedef union ii_itte1_u {
	bdrkreg_t	ii_itte1_regval;
	struct	{
		bdrkreg_t	i_rsvd			  :	51;
		bdrkreg_t	i_iosp			  :	 1;
		bdrkreg_t	i_w_num			  :	 4;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_offset		  :	 5;
	} ii_itte1_fld_s;
} ii_itte1_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Bedrock Big Window to a 48-bit       *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Bedrock is thus the lower 16 GBytes per widget    *
 * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
 * space can be accessed.                                               *
 * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
 * Window number) are used to select one of these 7 registers. The      *
 * Widget number field is then derived from the W_NUM field for         *
 * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
 * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
 * field is used as Crosstalk[47], and remainder of the Crosstalk       *
 * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
 * Crosstalk space addressable by the Bedrock is thus the lower         *
 * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
 * of this space can be accessed.                                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_itte2_u {
	bdrkreg_t	ii_itte2_regval;
	struct	{
		bdrkreg_t	i_offset		  :	 5;
		bdrkreg_t	i_rsvd_1		  :	 3;
		bdrkreg_t	i_w_num			  :	 4;
		bdrkreg_t	i_iosp			  :	 1;
		bdrkreg_t       i_rsvd                    :     51;
	} ii_itte2_fld_s;
} ii_itte2_u_t;

#else
typedef union ii_itte2_u {
	bdrkreg_t	ii_itte2_regval;
	struct  {
		bdrkreg_t	i_rsvd                    :	51;
		bdrkreg_t	i_iosp                    :	 1;
		bdrkreg_t	i_w_num                   :	 4;
		bdrkreg_t	i_rsvd_1                  :	 3;
		bdrkreg_t	i_offset                  :	 5;
	} ii_itte2_fld_s;
} ii_itte2_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  There are seven instances of translation table entry   *
 * registers. Each register maps a Bedrock Big Window to a 48-bit       *
 * address on Crosstalk.                                                *
 * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
 * number) are used to select one of these 7 registers. The Widget      *
 * number field is then derived from the W_NUM field for synthesizing   *
 * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
 * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
 * are padded with zeros. Although the maximum Crosstalk space          *
 * addressable by the Bedrock is thus the lower 16 GBytes per widget    *