hubio.h

上传linux-jx2410的源代码

#ifdef LITTLE_ENDIAN

typedef union ii_wid_u {
	bdrkreg_t	ii_wid_regval;
	struct	{
		bdrkreg_t	w_rsvd_1		  :	 1;
		bdrkreg_t	w_mfg_num		  :	11;
		bdrkreg_t	w_part_num		  :	16;
		bdrkreg_t	w_rev_num		  :	 4;
		bdrkreg_t	w_rsvd			  :	32;
	} ii_wid_fld_s;
} ii_wid_u_t;

#else

typedef union ii_wid_u {
	bdrkreg_t	ii_wid_regval;
	struct  {
		bdrkreg_t	w_rsvd                    :	32;
		bdrkreg_t	w_rev_num                 :	 4;
		bdrkreg_t	w_part_num                :	16;
		bdrkreg_t	w_mfg_num                 :	11;
		bdrkreg_t	w_rsvd_1                  :	 1;
	} ii_wid_fld_s;
} ii_wid_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  The fields in this register are set upon detection of an error      *
 * and cleared by various mechanisms, as explained in the               *
 * description.                                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_wstat_u {
	bdrkreg_t	ii_wstat_regval;
	struct	{
		bdrkreg_t	w_pending		  :	 4;
		bdrkreg_t	w_xt_crd_to		  :	 1;
		bdrkreg_t	w_xt_tail_to		  :	 1;
		bdrkreg_t	w_rsvd_3		  :	 3;
		bdrkreg_t       w_tx_mx_rty               :      1;
		bdrkreg_t	w_rsvd_2		  :	 6;
		bdrkreg_t	w_llp_tx_cnt		  :	 8;
		bdrkreg_t	w_rsvd_1		  :	 8;
		bdrkreg_t	w_crazy			  :	 1;
		bdrkreg_t	w_rsvd			  :	31;
	} ii_wstat_fld_s;
} ii_wstat_u_t;

#else

typedef union ii_wstat_u {
	bdrkreg_t	ii_wstat_regval;
	struct  {
		bdrkreg_t	w_rsvd                    :	31;
		bdrkreg_t	w_crazy                   :	 1;
		bdrkreg_t	w_rsvd_1                  :	 8;
		bdrkreg_t	w_llp_tx_cnt              :	 8;
		bdrkreg_t	w_rsvd_2                  :	 6;
		bdrkreg_t	w_tx_mx_rty               :	 1;
		bdrkreg_t	w_rsvd_3                  :	 3;
		bdrkreg_t	w_xt_tail_to              :	 1;
		bdrkreg_t	w_xt_crd_to               :	 1;
		bdrkreg_t	w_pending                 :	 4;
	} ii_wstat_fld_s;
} ii_wstat_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This is a read-write enabled register. It controls     *
 * various aspects of the Crosstalk flow control.                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_wcr_u {
	bdrkreg_t	ii_wcr_regval;
	struct	{
		bdrkreg_t	w_wid			  :	 4;
		bdrkreg_t	w_tag			  :	 1;
		bdrkreg_t	w_rsvd_1		  :	 8;
		bdrkreg_t	w_dst_crd		  :	 3;
		bdrkreg_t	w_f_bad_pkt		  :	 1;
		bdrkreg_t	w_dir_con		  :	 1;
		bdrkreg_t	w_e_thresh		  :	 5;
		bdrkreg_t	w_rsvd			  :	41;
	} ii_wcr_fld_s;
} ii_wcr_u_t;

#else

typedef union ii_wcr_u {
	bdrkreg_t	ii_wcr_regval;
	struct  {
		bdrkreg_t	w_rsvd                    :	41;
		bdrkreg_t	w_e_thresh                :	 5;
		bdrkreg_t	w_dir_con                 :	 1;
		bdrkreg_t	w_f_bad_pkt               :	 1;
		bdrkreg_t	w_dst_crd                 :	 3;
		bdrkreg_t	w_rsvd_1                  :	 8;
		bdrkreg_t	w_tag                     :	 1;
		bdrkreg_t	w_wid                     :	 4;
	} ii_wcr_fld_s;
} ii_wcr_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register's value is a bit vector that guards      *
 * access to local registers within the II as well as to external       *
 * Crosstalk widgets. Each bit in the register corresponds to a         *
 * particular region in the system; a region consists of one, two or    *
 * four nodes (depending on the value of the REGION_SIZE field in the   *
 * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
 * protection provided by this register applies to PIO read             *
 * operations as well as PIO write operations. The II will perform a    *
 * PIO read or write request only if the bit for the requestor's        *
 * region is set; otherwise, the II will not perform the requested      *
 * operation and will return an error response. When a PIO read or      *
 * write request targets an external Crosstalk widget, then not only    *
 * must the bit for the requestor's region be set in the ILAPR, but     *
 * also the target widget's bit in the IOWA register must be set in     *
 * order for the II to perform the requested operation; otherwise,      *
 * the II will return an error response. Hence, the protection          *
 * provided by the IOWA register supplements the protection provided    *
 * by the ILAPR for requests that target external Crosstalk widgets.    *
 * This register itself can be accessed only by the nodes whose         *
 * region ID bits are enabled in this same register. It can also be     *
 * accessed through the IAlias space by the local processors.           *
 * The reset value of this register allows access by all nodes.         *
 *                                                                      *
 ************************************************************************/




typedef union ii_ilapr_u {
	bdrkreg_t	ii_ilapr_regval;
	struct  {
		bdrkreg_t	i_region                  :	64;
	} ii_ilapr_fld_s;
} ii_ilapr_u_t;




/************************************************************************
 *                                                                      *
 * Description:  A write to this register of the 64-bit value           *
 * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
 * corresponding to the region of the requestor to be set (allow        *
 * access). A write of any other value will be ignored. Access          *
 * protection for this register is "SGIrules".                          *
 * This register can also be accessed through the IAlias space.         *
 * However, this access will not change the access permissions in the   *
 * ILAPR.                                                               *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_ilapo_u {
	bdrkreg_t	ii_ilapo_regval;
	struct	{
		bdrkreg_t	i_io_ovrride		  :	 9;
		bdrkreg_t	i_rsvd			  :	55;
	} ii_ilapo_fld_s;
} ii_ilapo_u_t;

#else

typedef union ii_ilapo_u {
	bdrkreg_t	ii_ilapo_regval;
	struct  {
		bdrkreg_t	i_rsvd                    :	55;
		bdrkreg_t	i_io_ovrride              :	 9;
	} ii_ilapo_fld_s;
} ii_ilapo_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register qualifies all the PIO and Graphics writes launched    *
 * from the Bedrock towards a widget.                                   *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_iowa_u {
	bdrkreg_t	ii_iowa_regval;
	struct	{
		bdrkreg_t	i_w0_oac		  :	 1;
		bdrkreg_t	i_rsvd_1		  :	 7;
                bdrkreg_t       i_wx_oac                  :      8;
		bdrkreg_t	i_rsvd			  :	48;
	} ii_iowa_fld_s;
} ii_iowa_u_t;

#else

typedef union ii_iowa_u {
	bdrkreg_t	ii_iowa_regval;
	struct  {
		bdrkreg_t	i_rsvd                    :	48;
		bdrkreg_t	i_wx_oac                  :	 8;
		bdrkreg_t	i_rsvd_1                  :	 7;
		bdrkreg_t	i_w0_oac                  :	 1;
	} ii_iowa_fld_s;
} ii_iowa_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register qualifies all the requests launched      *
 * from a widget towards the Bedrock. This register is intended to be   *
 * used by software in case of misbehaving widgets.                     *
 *                                                                      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_iiwa_u {
	bdrkreg_t	ii_iiwa_regval;
	struct  {
		bdrkreg_t	i_w0_iac                  :	 1;
		bdrkreg_t	i_rsvd_1		  :	 7;
		bdrkreg_t	i_wx_iac		  :	 8;
		bdrkreg_t	i_rsvd			  :	48;
	} ii_iiwa_fld_s;
} ii_iiwa_u_t;

#else

typedef union ii_iiwa_u {
	bdrkreg_t	ii_iiwa_regval;
	struct	{
		bdrkreg_t	i_rsvd			  :	48;
		bdrkreg_t	i_wx_iac		  :	 8;
		bdrkreg_t	i_rsvd_1		  :	 7;
		bdrkreg_t	i_w0_iac		  :	 1;
	} ii_iiwa_fld_s;
} ii_iiwa_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register qualifies all the operations launched    *
 * from a widget towards the Bedrock. It allows individual access       *
 * control for up to 8 devices per widget. A device refers to           *
 * individual DMA master hosted by a widget.                            *
 * The bits in each field of this register are cleared by the Bedrock   *
 * upon detection of an error which requires the device to be           *
 * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
 * Crosstalk). Whether or not a device has access rights to this        *
 * Bedrock is determined by an AND of the device enable bit in the      *
 * appropriate field of this register and the corresponding bit in      *
 * the Wx_IAC field (for the widget which this device belongs to).      *
 * The bits in this field are set by writing a 1 to them. Incoming      *
 * replies from Crosstalk are not subject to this access control        *
 * mechanism.                                                           *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_iidem_u {
	bdrkreg_t	ii_iidem_regval;
	struct	{
		bdrkreg_t	i_w8_dxs		  :	 8;
		bdrkreg_t	i_w9_dxs		  :	 8;
		bdrkreg_t	i_wa_dxs		  :	 8;
		bdrkreg_t	i_wb_dxs		  :	 8;
		bdrkreg_t	i_wc_dxs		  :	 8;
		bdrkreg_t	i_wd_dxs		  :	 8;
		bdrkreg_t	i_we_dxs		  :	 8;
		bdrkreg_t	i_wf_dxs		  :	 8;
	} ii_iidem_fld_s;
} ii_iidem_u_t;

#else

typedef union ii_iidem_u {
	bdrkreg_t	ii_iidem_regval;
	struct  {
		bdrkreg_t	i_wf_dxs                  :	 8;
		bdrkreg_t	i_we_dxs                  :	 8;
		bdrkreg_t	i_wd_dxs                  :	 8;
		bdrkreg_t	i_wc_dxs                  :	 8;
		bdrkreg_t	i_wb_dxs                  :	 8;
		bdrkreg_t	i_wa_dxs                  :	 8;
		bdrkreg_t	i_w9_dxs                  :	 8;
		bdrkreg_t	i_w8_dxs                  :	 8;
	} ii_iidem_fld_s;
} ii_iidem_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register contains the various programmable fields necessary    *
 * for controlling and observing the LLP signals.                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union ii_ilcsr_u {
	bdrkreg_t	ii_ilcsr_regval;
	struct  {
		bdrkreg_t	i_nullto                  :	 6;
		bdrkreg_t	i_rsvd_4		  :	 2;
		bdrkreg_t	i_wrmrst		  :	 1;
		bdrkreg_t	i_rsvd_3		  :	 1;
		bdrkreg_t	i_llp_en		  :	 1;
		bdrkreg_t	i_bm8			  :	 1;
		bdrkreg_t	i_llp_stat		  :	 2;
		bdrkreg_t	i_remote_power		  :	 1;
		bdrkreg_t	i_rsvd_2		  :	 1;
		bdrkreg_t	i_maxrtry		  :	10;
		bdrkreg_t	i_d_avail_sel		  :	 2;
		bdrkreg_t	i_rsvd_1		  :	 4;
		bdrkreg_t	i_maxbrst		  :	10;
                bdrkreg_t       i_rsvd                    :     22;

	} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;

#else

typedef union ii_ilcsr_u {
	bdrkreg_t	ii_ilcsr_regval;