hublb.h

上传linux-jx2410的源代码

 * <LI >RQ_LONG for an incoming request with expected data.             *
 * <BLOCKQUOTE >                                                        *
 * In the case of RQ_BAD_LINVAL, the register retains the 64-bit data   *
 * value that followed the header flit.  In the case of RQ_BAD_ADDR     *
 * or RQ_BAD_DATA, the register retains the incoming packet's 64-bit    *
 * data value (i.e., 2nd flit in the packet for a normal PIO write or   *
 * an LINVAL, 3rd flit for a vector PIO read or write). In the case     *
 * of RP_BAD_DATA, the register retains the 64-bit data value in the    *
 * 3rd flit of the packet. When a RP_LONG or RQ_LONG error occurs,      *
 * the LB loads the LB_ERROR_DATA register with the contents of the     *
 * expected data flit (i.e., the 3rd flit in the packet for a vector    *
 * PIO request or reply, the 2nd flit for other packets), if any. The   *
 * contents of the LB_ERROR_DATA register are undefined after a         *
 * RP_SHORT, RQ_SHORT, RP_BAD_CMD or RQ_BAD_CMD error. The contents     *
 * of the LB_ERROR_DATA register are also undefined after an incoming   *
 * normal PIO read request which encounters a RQ_LONG error.            *
 *                                                                      *
 ************************************************************************/




typedef union lb_error_data_u {
	bdrkreg_t	lb_error_data_regval;
	struct  {
		bdrkreg_t	ed_data                   :	64;
	} lb_error_data_fld_s;
} lb_error_data_u_t;




/************************************************************************
 *                                                                      *
 *  This register enables software to control what internal Bedrock     *
 * signals are visible on the chip's debug pins. The LB provides the    *
 * 6-bit value in this register to Bedrock's DEBUG unit. The JTAG       *
 * unit provides a similar 6-bit selection input to the DEBUG unit,     *
 * along with another signal that tells the DEBUG unit whether to use   *
 * the selection signal from the LB or the JTAG unit. For a             *
 * description of the menu of choices for debug signals, refer to the   *
 * documentation for the DEBUG unit.                                    *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_debug_select_u {
	bdrkreg_t	lb_debug_select_regval;
	struct  {
		bdrkreg_t	ds_debug_sel              :	 6;
		bdrkreg_t       ds_reserved               :     58;
	} lb_debug_select_fld_s;
} lb_debug_select_u_t;

#else

typedef union lb_debug_select_u {
	bdrkreg_t	lb_debug_select_regval;
	struct	{
		bdrkreg_t	ds_reserved		  :	58;
		bdrkreg_t	ds_debug_sel		  :	 6;
	} lb_debug_select_fld_s;
} lb_debug_select_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  A PIO read from this register returns the 32-bit value that is      *
 * currently on the Bedrock chip's debug pins. This register allows     *
 * software to observe debug pin output values which do not change      *
 * frequently (i.e., they remain constant over a period of many         *
 * cycles).                                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_debug_pins_u {
	bdrkreg_t	lb_debug_pins_regval;
	struct  {
		bdrkreg_t	dp_debug_pins             :	32;
		bdrkreg_t       dp_reserved               :     32;
	} lb_debug_pins_fld_s;
} lb_debug_pins_u_t;

#else

typedef union lb_debug_pins_u {
	bdrkreg_t	lb_debug_pins_regval;
	struct	{
		bdrkreg_t	dp_reserved		  :	32;
		bdrkreg_t	dp_debug_pins		  :	32;
	} lb_debug_pins_fld_s;
} lb_debug_pins_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  The LB unit provides the PI0 and PI1 units with a real-time clock   *
 * signal. The LB can generate this signal itself, based on the         *
 * Bedrock chip's system clock which the LB receives as an input.       *
 * Alternatively, the LB can filter a global clock signal which it      *
 * receives as an input and provide the filtered version to PI0 and     *
 * PI1. The user can program the LB_RT_LOCAL_CTRL register to choose    *
 * the source of the real-time clock. If the user chooses to generate   *
 * the real-time clock internally within the LB, then the user can      *
 * specify the period for the real-time clock signal.                   *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_rt_local_ctrl_u {
	bdrkreg_t	lb_rt_local_ctrl_regval;
	struct  {
		bdrkreg_t	rlc_gclk_enable           :	 1;
		bdrkreg_t       rlc_reserved_4            :      3;
		bdrkreg_t       rlc_max_count             :     10;
		bdrkreg_t       rlc_reserved_3            :      2;
		bdrkreg_t       rlc_gclk_counter          :     10;
		bdrkreg_t       rlc_reserved_2            :      2;
		bdrkreg_t       rlc_gclk                  :      1;
		bdrkreg_t       rlc_reserved_1            :      3;
		bdrkreg_t       rlc_use_internal          :      1;
		bdrkreg_t       rlc_reserved              :     31;
	} lb_rt_local_ctrl_fld_s;
} lb_rt_local_ctrl_u_t;

#else

typedef union lb_rt_local_ctrl_u {
        bdrkreg_t       lb_rt_local_ctrl_regval;
        struct  {
                bdrkreg_t       rlc_reserved              :     31;
                bdrkreg_t       rlc_use_internal          :      1;
                bdrkreg_t       rlc_reserved_1            :      3;
                bdrkreg_t       rlc_gclk                  :      1;
                bdrkreg_t       rlc_reserved_2            :      2;
                bdrkreg_t       rlc_gclk_counter          :     10;
                bdrkreg_t       rlc_reserved_3            :      2;
                bdrkreg_t       rlc_max_count             :     10;
                bdrkreg_t       rlc_reserved_4            :      3;
                bdrkreg_t       rlc_gclk_enable           :      1;
        } lb_rt_local_ctrl_fld_s;
} lb_rt_local_ctrl_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  When the value of the USE_INTERNAL field in the LB_RT_LOCAL_CTRL    *
 * register is 0, the LB filters an incoming global clock signal and    *
 * provides the result to PI0 and PI1 for their real-time clock         *
 * inputs. The LB can perform either simple filtering or complex        *
 * filtering, depending on the value of the MASK_ENABLE bit. For the    *
 * simple filtering option, the LB merely removes glitches from the     *
 * incoming global clock; if the global clock goes high (or low) for    *
 * only a single cycle, the LB considers it to be a glitch and does     *
 * not pass it through to PI0 and PI1. For the complex filtering        *
 * option, the LB expects positive edges on the incoming global clock   *
 * to be spaced at fairly regular intervals and it looks for them at    *
 * these times; the LB keeps track of unexpected or missing positive    *
 * edges, and it generates an edge itself whenever the incoming         *
 * global clock apparently misses an edge. For each filtering option,   *
 * the real-time clock which the LB provides to PI0 and PI1 is not      *
 * necessarily a square wave; when a positive edge happens, the         *
 * real-time clock stays high for (2*MAX_COUNT+1-OFFSET)/2 cycles of    *
 * the LB's system clock, and then is low until the next positive       *
 * edge.                                                                *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_rt_filter_ctrl_u {
	bdrkreg_t	lb_rt_filter_ctrl_regval;
	struct  {
		bdrkreg_t       rfc_offset                :      5;
		bdrkreg_t       rfc_reserved_4            :      3;
		bdrkreg_t       rfc_mask_counter          :     12;
		bdrkreg_t       rfc_mask_enable           :      1;
		bdrkreg_t       rfc_reserved_3            :      3;
		bdrkreg_t       rfc_dropout_counter       :     10;
		bdrkreg_t       rfc_reserved_2            :      2;
		bdrkreg_t       rfc_dropout_thresh        :     10;
		bdrkreg_t       rfc_reserved_1            :      2;
		bdrkreg_t       rfc_error_counter         :     10;
		bdrkreg_t       rfc_reserved              :      6;
	} lb_rt_filter_ctrl_fld_s;
} lb_rt_filter_ctrl_u_t;

#else

typedef union lb_rt_filter_ctrl_u {
        bdrkreg_t       lb_rt_filter_ctrl_regval;
        struct  {
                bdrkreg_t       rfc_reserved              :      6;
                bdrkreg_t       rfc_error_counter         :     10;
                bdrkreg_t       rfc_reserved_1            :      2;
                bdrkreg_t       rfc_dropout_thresh        :     10;
                bdrkreg_t       rfc_reserved_2            :      2;
                bdrkreg_t       rfc_dropout_counter       :     10;
                bdrkreg_t       rfc_reserved_3            :      3;
                bdrkreg_t       rfc_mask_enable           :      1;
                bdrkreg_t       rfc_mask_counter          :     12;
                bdrkreg_t       rfc_reserved_4            :      3;
                bdrkreg_t       rfc_offset                :      5;
        } lb_rt_filter_ctrl_fld_s;
} lb_rt_filter_ctrl_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register is a scratch register that is reset to 0x0. At the    *
 * normal address, the register is a simple storage location. At the    *
 * Write-If-Zero address, the register accepts a new value from a       *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg0_u {
	bdrkreg_t	lb_scratch_reg0_regval;
	struct  {
		bdrkreg_t	sr_scratch_bits           :	64;
	} lb_scratch_reg0_fld_s;
} lb_scratch_reg0_u_t;




/************************************************************************
 *                                                                      *
 *  These registers are scratch registers that are not reset. At a      *
 * register's normal address, it is a simple storage location. At a     *
 * register's Write-If-Zero address, it accepts a new value from a      *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg1_u {
	bdrkreg_t	lb_scratch_reg1_regval;
	struct  {
		bdrkreg_t	sr_scratch_bits           :	64;
	} lb_scratch_reg1_fld_s;
} lb_scratch_reg1_u_t;




/************************************************************************
 *                                                                      *
 *  These registers are scratch registers that are not reset. At a      *
 * register's normal address, it is a simple storage location. At a     *
 * register's Write-If-Zero address, it accepts a new value from a      *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg2_u {
	bdrkreg_t	lb_scratch_reg2_regval;
	struct  {
		bdrkreg_t	sr_scratch_bits           :	64;
	} lb_scratch_reg2_fld_s;
} lb_scratch_reg2_u_t;




/************************************************************************
 *                                                                      *
 *  These one-bit registers are scratch registers. At a register's      *
 * normal address, it is a simple storage location. At a register's     *
 * Read-Set-If-Zero address, it returns the original contents and       *
 * sets the bit if the original value is zero.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_scratch_reg3_u {
	bdrkreg_t	lb_scratch_reg3_regval;
	struct  {
		bdrkreg_t	sr_scratch_bit            :	 1;
		bdrkreg_t	sr_reserved		  :	63;
	} lb_scratch_reg3_fld_s;
} lb_scratch_reg3_u_t;

#else

typedef union lb_scratch_reg3_u {
	bdrkreg_t	lb_scratch_reg3_regval;
	struct	{
		bdrkreg_t	sr_reserved		  :	63;
		bdrkreg_t	sr_scratch_bit		  :	 1;
	} lb_scratch_reg3_fld_s;
} lb_scratch_reg3_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  These one-bit registers are scratch registers. At a register's      *
 * normal address, it is a simple storage location. At a register's     *
 * Read-Set-If-Zero address, it returns the original contents and       *
 * sets the bit if the original value is zero.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_scratch_reg4_u {
	bdrkreg_t	lb_scratch_reg4_regval;
	struct  {
		bdrkreg_t	sr_scratch_bit            :	 1;
		bdrkreg_t       sr_reserved               :     63;
	} lb_scratch_reg4_fld_s;
} lb_scratch_reg4_u_t;

#else

typedef union lb_scratch_reg4_u {
	bdrkreg_t	lb_scratch_reg4_regval;
	struct	{
		bdrkreg_t	sr_reserved		  :	63;
		bdrkreg_t	sr_scratch_bit		  :	 1;
	} lb_scratch_reg4_fld_s;
} lb_scratch_reg4_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register is a scratch register that is reset to 0x0. At the    *
 * normal address, the register is a simple storage location. At the    *
 * Write-If-Zero address, the register accepts a new value from a       *
 * write operation only if the current value is zero.                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_scratch_reg0_wz_u {
	bdrkreg_t	lb_scratch_reg0_wz_regval;
	struct  {
		bdrkreg_t	srw_scratch_bits          :	64;
	} lb_scratch_reg0_wz_fld_s;
} lb_scratch_reg0_wz_u_t;




/************************************************************************
 *                                                                      *