hublb.h

上传linux-jx2410的源代码

#else

typedef union lb_soft_reset_u {
	bdrkreg_t	lb_soft_reset_regval;
	struct	{
		bdrkreg_t	sr_reserved		  :	63;
		bdrkreg_t	sr_soft_reset		  :	 1;
	} lb_soft_reset_fld_s;
} lb_soft_reset_u_t;

#endif



/************************************************************************
 *                                                                      *
 *  This register indicates which regions are present and capable of    *
 * receiving an invalidate (INVAL) request. The LB samples this         *
 * register at the start of processing each LINVAL. When an LINVAL      *
 * indicates that a particular PI unit might hold a shared copy of a    *
 * cache block but this PI is in a region which is not present (i.e.,   *
 * its bit in LB_REGION_PRESENT is clear), then the LB sends an IVACK   *
 * reply packet on behalf of this PI. The REGION_SIZE field in the      *
 * LB_REV_ID register determines the number of nodes per region (and    *
 * hence, the number of PI units which share a common bit in the        *
 * LB_REGION_PRESENT register).                                         *
 *                                                                      *
 ************************************************************************/




typedef union lb_region_present_u {
	bdrkreg_t	lb_region_present_regval;
	struct  {
		bdrkreg_t	rp_present_bits           :	64;
	} lb_region_present_fld_s;
} lb_region_present_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This register indicates which nodes are absent and     *
 * not capable of receiving an invalidate (INVAL) request. The LB       *
 * samples this register at the start of processing each LINVAL. When   *
 * an LINVAL indicates that a particular PI unit might hold a shared    *
 * copy of a cache block but this PI unit's node is not present         *
 * (i.e., its node ID is listed in the LB_NODES_ABSENT register),       *
 * then the LB sends an IVACK reply packet on behalf of this PI.        *
 *                                                                      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_nodes_absent_u {
	bdrkreg_t	lb_nodes_absent_regval;
	struct  {
		bdrkreg_t	na_node_0                 :	 8;
		bdrkreg_t       na_reserved_3             :      7;
		bdrkreg_t       na_node_0_valid           :      1;
		bdrkreg_t       na_node_1                 :      8;
		bdrkreg_t       na_reserved_2             :      7;
		bdrkreg_t       na_node_1_valid           :      1;
		bdrkreg_t       na_node_2                 :      8;
		bdrkreg_t       na_reserved_1             :      7;
		bdrkreg_t       na_node_2_valid           :      1;
		bdrkreg_t       na_node_3                 :      8;
		bdrkreg_t       na_reserved               :      7;
		bdrkreg_t       na_node_3_valid           :      1;
	} lb_nodes_absent_fld_s;
} lb_nodes_absent_u_t;

#else

typedef union lb_nodes_absent_u {
	bdrkreg_t	lb_nodes_absent_regval;
	struct	{
		bdrkreg_t	na_node_3_valid		  :	 1;
		bdrkreg_t	na_reserved		  :	 7;
		bdrkreg_t	na_node_3		  :	 8;
		bdrkreg_t	na_node_2_valid		  :	 1;
		bdrkreg_t	na_reserved_1		  :	 7;
		bdrkreg_t	na_node_2		  :	 8;
		bdrkreg_t	na_node_1_valid		  :	 1;
		bdrkreg_t	na_reserved_2		  :	 7;
		bdrkreg_t	na_node_1		  :	 8;
		bdrkreg_t	na_node_0_valid		  :	 1;
		bdrkreg_t	na_reserved_3		  :	 7;
		bdrkreg_t	na_node_0		  :	 8;
	} lb_nodes_absent_fld_s;
} lb_nodes_absent_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register provides access to the Number-In-a-Can add-only       *
 * serial PROM that is used to store node board serial number and       *
 * configuration information. (Refer to NIC datasheet Dallas 1990A      *
 * that is viewable at                                                  *
 * URL::http://www.dalsemi.com/DocControl/PDFs/pdfindex.html). Data     *
 * comes from this interface LSB first.                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_microlan_ctl_u {
	bdrkreg_t	lb_microlan_ctl_regval;
	struct  {
		bdrkreg_t	mc_rd_data                :	 1;
		bdrkreg_t       mc_done                   :      1;
		bdrkreg_t       mc_sample                 :      8;
		bdrkreg_t       mc_pulse                  :     10;
		bdrkreg_t       mc_clkdiv_phi0            :      7;
		bdrkreg_t       mc_clkdiv_phi1            :      7;
		bdrkreg_t       mc_reserved               :     30;
	} lb_microlan_ctl_fld_s;
} lb_microlan_ctl_u_t;

#else

typedef union lb_microlan_ctl_u {
        bdrkreg_t       lb_microlan_ctl_regval;
        struct  {
                bdrkreg_t       mc_reserved               :     30;
                bdrkreg_t       mc_clkdiv_phi1            :      7;
                bdrkreg_t       mc_clkdiv_phi0            :      7;
                bdrkreg_t       mc_pulse                  :     10;
                bdrkreg_t       mc_sample                 :      8;
                bdrkreg_t       mc_done                   :      1;
                bdrkreg_t       mc_rd_data                :      1;
        } lb_microlan_ctl_fld_s;
} lb_microlan_ctl_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register contains the LB error status bits.       *
 * Whenever a particular type of error occurs, the LB sets its bit in   *
 * this register so that software will be aware that such an event      *
 * has happened. Reads from this register are non-destructive and the   *
 * contents of this register remain intact across reset operations.     *
 * Whenever any of these bits is set, the LB will assert its            *
 * interrupt request output signals that go to the PI units.            *
 *  Software can simulate the occurrence of an error by first writing   *
 * appropriate values into the LB_ERROR_HDR1, LB_ERROR_HDR2 and         *
 * LB_ERROR_DATA registers, and then writing to the LB_ERROR_BITS       *
 * register to set the error bits in a particular way. Setting one or   *
 * more error bits will cause the LB to interrupt a processor and       *
 * invoke error-handling software.                                      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_error_bits_u {
	bdrkreg_t	lb_error_bits_regval;
	struct  {
		bdrkreg_t	eb_rq_bad_cmd             :	 1;
		bdrkreg_t       eb_rp_bad_cmd             :      1;
		bdrkreg_t       eb_rq_short               :      1;
		bdrkreg_t       eb_rp_short               :      1;
		bdrkreg_t       eb_rq_long                :      1;
		bdrkreg_t       eb_rp_long                :      1;
		bdrkreg_t       eb_rq_bad_data            :      1;
		bdrkreg_t       eb_rp_bad_data            :      1;
		bdrkreg_t       eb_rq_bad_addr            :      1;
		bdrkreg_t       eb_rq_bad_linval          :      1;
		bdrkreg_t       eb_gclk_drop              :      1;
		bdrkreg_t       eb_reserved               :     53;
	} lb_error_bits_fld_s;
} lb_error_bits_u_t;

#else

typedef union lb_error_bits_u {
	bdrkreg_t	lb_error_bits_regval;
	struct	{
		bdrkreg_t	eb_reserved		  :	53;
		bdrkreg_t	eb_gclk_drop		  :	 1;
		bdrkreg_t	eb_rq_bad_linval	  :	 1;
		bdrkreg_t	eb_rq_bad_addr		  :	 1;
		bdrkreg_t	eb_rp_bad_data		  :	 1;
		bdrkreg_t	eb_rq_bad_data		  :	 1;
		bdrkreg_t	eb_rp_long		  :	 1;
		bdrkreg_t	eb_rq_long		  :	 1;
		bdrkreg_t	eb_rp_short		  :	 1;
		bdrkreg_t	eb_rq_short		  :	 1;
		bdrkreg_t	eb_rp_bad_cmd		  :	 1;
		bdrkreg_t	eb_rq_bad_cmd		  :	 1;
	} lb_error_bits_fld_s;
} lb_error_bits_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register lets software clear some of the bits in the           *
 * LB_ERROR_BITS register without affecting other bits.  Essentially,   *
 * it provides bit mask functionality. When software writes to the      *
 * LB_ERROR_MASK_CLR register, the bits which are set in the data       *
 * value indicate which bits are to be cleared in LB_ERROR_BITS. If a   *
 * bit is clear in the data value written to the LB_ERROR_MASK_CLR      *
 * register, then its corresponding bit in the LB_ERROR_BITS register   *
 * is not affected. Hence, software can atomically clear any subset     *
 * of the error bits in the LB_ERROR_BITS register.                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_error_mask_clr_u {
	bdrkreg_t	lb_error_mask_clr_regval;
	struct  {
		bdrkreg_t	emc_clr_rq_bad_cmd        :	 1;
		bdrkreg_t       emc_clr_rp_bad_cmd        :      1;
		bdrkreg_t       emc_clr_rq_short          :      1;
		bdrkreg_t       emc_clr_rp_short          :      1;
		bdrkreg_t       emc_clr_rq_long           :      1;
		bdrkreg_t       emc_clr_rp_long           :      1;
		bdrkreg_t       emc_clr_rq_bad_data       :      1;
		bdrkreg_t       emc_clr_rp_bad_data       :      1;
		bdrkreg_t       emc_clr_rq_bad_addr       :      1;
		bdrkreg_t       emc_clr_rq_bad_linval     :      1;
		bdrkreg_t       emc_clr_gclk_drop         :      1;
		bdrkreg_t       emc_reserved              :     53;
	} lb_error_mask_clr_fld_s;
} lb_error_mask_clr_u_t;

#else

typedef union lb_error_mask_clr_u {
	bdrkreg_t	lb_error_mask_clr_regval;
	struct	{
		bdrkreg_t	emc_reserved		  :	53;
		bdrkreg_t	emc_clr_gclk_drop	  :	 1;
		bdrkreg_t	emc_clr_rq_bad_linval	  :	 1;
		bdrkreg_t	emc_clr_rq_bad_addr	  :	 1;
		bdrkreg_t	emc_clr_rp_bad_data	  :	 1;
		bdrkreg_t	emc_clr_rq_bad_data	  :	 1;
		bdrkreg_t	emc_clr_rp_long		  :	 1;
		bdrkreg_t	emc_clr_rq_long		  :	 1;
		bdrkreg_t	emc_clr_rp_short	  :	 1;
		bdrkreg_t	emc_clr_rq_short	  :	 1;
		bdrkreg_t	emc_clr_rp_bad_cmd	  :	 1;
		bdrkreg_t	emc_clr_rq_bad_cmd	  :	 1;
	} lb_error_mask_clr_fld_s;
} lb_error_mask_clr_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  If the LB detects an error when VALID==0 in the LB_ERROR_HDR1       *
 * register, then it saves the contents of the offending packet's       *
 * header flit in the LB_ERROR_HDR1 and LB_ERROR_HDR2 registers, sets   *
 * the VALID bit in LB_ERROR_HDR1 and clears the OVERRUN bit in         *
 * LB_ERROR_HDR1 (and it will also set the corresponding bit in the     *
 * LB_ERROR_BITS register). The ERR_TYPE field indicates specifically   *
 * what kind of error occurred.  Its encoding corresponds to the bit    *
 * positions in the LB_ERROR_BITS register (e.g., ERR_TYPE==5           *
 * indicates a RP_LONG error).  If an error (of any type except         *
 * GCLK_DROP) subsequently happens while VALID==1, then the LB sets     *
 * the OVERRUN bit in LB_ERROR_HDR1. This register is not relevant      *
 * when a GCLK_DROP error occurs; the LB does not even attempt to       *
 * change the ERR_TYPE, VALID or OVERRUN field when a GCLK_DROP error   *
 * happens.                                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_error_hdr1_u {
	bdrkreg_t	lb_error_hdr1_regval;
	struct  {
		bdrkreg_t	eh_command                :	 7;
		bdrkreg_t       eh_reserved_5             :      1;
		bdrkreg_t       eh_suppl                  :     11;
		bdrkreg_t       eh_reserved_4             :      1;
		bdrkreg_t       eh_source                 :     11;
		bdrkreg_t       eh_reserved_3             :      1;
		bdrkreg_t       eh_err_type               :      4;
		bdrkreg_t       eh_reserved_2             :      4;
		bdrkreg_t       eh_overrun                :      1;
		bdrkreg_t       eh_reserved_1             :      3;
		bdrkreg_t       eh_valid                  :      1;
		bdrkreg_t       eh_reserved               :     19;
	} lb_error_hdr1_fld_s;
} lb_error_hdr1_u_t;

#else

typedef union lb_error_hdr1_u {
	bdrkreg_t	lb_error_hdr1_regval;
	struct	{
		bdrkreg_t	eh_reserved		  :	19;
		bdrkreg_t	eh_valid		  :	 1;
		bdrkreg_t	eh_reserved_1		  :	 3;
		bdrkreg_t	eh_overrun		  :	 1;
		bdrkreg_t	eh_reserved_2		  :	 4;
		bdrkreg_t	eh_err_type		  :	 4;
		bdrkreg_t	eh_reserved_3		  :	 1;
		bdrkreg_t	eh_source		  :	11;
		bdrkreg_t	eh_reserved_4		  :	 1;
		bdrkreg_t	eh_suppl		  :	11;
		bdrkreg_t	eh_reserved_5		  :	 1;
		bdrkreg_t	eh_command		  :	 7;
	} lb_error_hdr1_fld_s;
} lb_error_hdr1_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Contents of the Address field from header flit of first packet      *
 * that causes an error. This register is not relevant when a           *
 * GCLK_DROP error occurs.                                              *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_error_hdr2_u {
	bdrkreg_t	lb_error_hdr2_regval;
	struct  {
		bdrkreg_t	eh_address                :	38;
		bdrkreg_t       eh_reserved               :     26;
	} lb_error_hdr2_fld_s;
} lb_error_hdr2_u_t;

#else

typedef union lb_error_hdr2_u {
	bdrkreg_t	lb_error_hdr2_regval;
	struct	{
		bdrkreg_t	eh_reserved		  :	26;
		bdrkreg_t	eh_address		  :	38;
	} lb_error_hdr2_fld_s;
} lb_error_hdr2_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register accompanies the LB_ERROR_HDR1 and        *
 * LB_ERROR_HDR2 registers.  The LB updates the value in this           *
 * register when an incoming packet with a data flit causes an error    *
 * while VALID==0 in the LB_ERROR_HDR1 register.  This register         *
 * retains the contents of the data flit from the incoming packet       *
 * that caused the error. This register is relevant for the following   *
 * types of errors:                                                     *
 * <UL >                                                                *
 * <UL >                                                                *
 * <UL >                                                                *
 * <UL >                                                                *
 * <UL >                                                                *
 * <LI >RQ_BAD_LINVAL for a LINVAL request.                             *
 * <LI >RQ_BAD_ADDR for a normal or vector PIO request.                 *
 * <LI >RP_BAD_DATA for a vector PIO reply.                             *
 * <LI >RQ_BAD DATA for an incoming request with data.                  *
 * <LI >RP_LONG for a vector PIO reply.                                 *