hublb.h

上传linux-jx2410的源代码

/* $Id: hublb.h,v 1.1.1.1 2004/02/04 12:57:43 laputa Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2000 by Colin Ngam
 */

/************************************************************************
 *                                                                      *
 *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
 *                                                                      *
 * This file is created by an automated script. Any (minimal) changes   *
 * made manually to this  file should be made with care.                *
 *                                                                      *
 *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
 *                                                                      *
 ************************************************************************/


#ifndef _ASM_SN_SN1_HUBLB_H
#define _ASM_SN_SN1_HUBLB_H


#define    LB_REV_ID                 0x00600000    /*
                                                    * Bedrock Revision
                                                    * and ID
                                                    */



#define    LB_CPU_PERMISSION         0x00604000    /*
                                                    * CPU PIO access
                                                    * permission bits
                                                    */



#define    LB_CPU_PERM_OVRRD         0x00604008    /*
                                                    * CPU PIO access
                                                    * permission bit
                                                    * override
                                                    */



#define    LB_IO_PERMISSION          0x00604010    /*
                                                    * IO PIO access
                                                    * permission bits
                                                    */



#define    LB_SOFT_RESET             0x00604018    /*
                                                    * Soft reset the
                                                    * Bedrock chip
                                                    */



#define    LB_REGION_PRESENT         0x00604020    /*
                                                    * Regions Present for
                                                    * Invalidates
                                                    */



#define    LB_NODES_ABSENT           0x00604028    /*
                                                    * Nodes Absent for
                                                    * Invalidates
                                                    */



#define    LB_MICROLAN_CTL           0x00604030    /*
                                                    * Microlan Control
                                                    * (NIC)
                                                    */



#define    LB_ERROR_BITS             0x00604040    /*
                                                    * Local Block error
                                                    * bits
                                                    */



#define    LB_ERROR_MASK_CLR         0x00604048    /*
                                                    * Bit mask write to
                                                    * clear error bits
                                                    */



#define    LB_ERROR_HDR1             0x00604050    /*
                                                    * Source, Suppl and
                                                    * Cmd fields
                                                    */



#define    LB_ERROR_HDR2             0x00604058    /*
                                                    * Address field from
                                                    * first error
                                                    */



#define    LB_ERROR_DATA             0x00604060    /*
                                                    * Data flit (if any)
                                                    * from first error
                                                    */



#define    LB_DEBUG_SELECT           0x00604100    /*
                                                    * Choice of debug
                                                    * signals from chip
                                                    */



#define    LB_DEBUG_PINS             0x00604108    /*
                                                    * Value on the chip's
                                                    * debug pins
                                                    */



#define    LB_RT_LOCAL_CTRL          0x00604200    /*
                                                    * Local generation of
                                                    * real-time clock
                                                    */



#define    LB_RT_FILTER_CTRL         0x00604208    /*
                                                    * Control of
                                                    * filtering of global
                                                    * clock
                                                    */



#define    LB_SCRATCH_REG0           0x00608000    /* Scratch Register 0     */



#define    LB_SCRATCH_REG1           0x00608008    /* Scratch Register 1     */



#define    LB_SCRATCH_REG2           0x00608010    /* Scratch Register 2     */



#define    LB_SCRATCH_REG3           0x00608018    /* Scratch Register 3     */



#define    LB_SCRATCH_REG4           0x00608020    /* Scratch Register 4     */



#define    LB_SCRATCH_REG0_WZ        0x00608040    /*
                                                    * Scratch Register 0
                                                    * (WZ alias)
                                                    */



#define    LB_SCRATCH_REG1_WZ        0x00608048    /*
                                                    * Scratch Register 1
                                                    * (WZ alias)
                                                    */



#define    LB_SCRATCH_REG2_WZ        0x00608050    /*
                                                    * Scratch Register 2
                                                    * (WZ alias)
                                                    */



#define    LB_SCRATCH_REG3_RZ        0x00608058    /*
                                                    * Scratch Register 3
                                                    * (RZ alias)
                                                    */



#define    LB_SCRATCH_REG4_RZ        0x00608060    /*
                                                    * Scratch Register 4
                                                    * (RZ alias)
                                                    */



#define    LB_VECTOR_PARMS           0x0060C000    /*
                                                    * Vector PIO
                                                    * parameters
                                                    */



#define    LB_VECTOR_ROUTE           0x0060C008    /*
                                                    * Vector PIO Vector
                                                    * Route
                                                    */



#define    LB_VECTOR_DATA            0x0060C010    /*
                                                    * Vector PIO Write
                                                    * Data
                                                    */



#define    LB_VECTOR_STATUS          0x0060C020    /*
                                                    * Vector PIO Return
                                                    * Status
                                                    */



#define    LB_VECTOR_RETURN          0x0060C028    /*
                                                    * Vector PIO Return
                                                    * Route
                                                    */



#define    LB_VECTOR_READ_DATA       0x0060C030    /*
                                                    * Vector PIO Read
                                                    * Data
                                                    */



#define    LB_VECTOR_STATUS_CLEAR    0x0060C038    /*
                                                    * Clear Vector PIO
                                                    * Return Status
                                                    */





#ifdef _LANGUAGE_C

/************************************************************************
 *                                                                      *
 * Description:  This register contains information that allows         *
 * exploratory software to probe for chip type. This is also the        *
 * register that sets this node's ID and the size of each region        *
 * (which affects the maximum possible system size). IBM assigns the    *
 * values for the REVISION, PART_NUMBER and MANUFACTURER fields, in     *
 * accordance with the IEEE 1149.1 standard; SGI is not at liberty to   *
 * unilaterally change the values of these fields.                      *
 *  .                                                                   *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_rev_id_u {
	bdrkreg_t	lb_rev_id_regval;
	struct  {
		bdrkreg_t	ri_reserved_2             :	 1;
		bdrkreg_t       ri_manufacturer           :     11;
		bdrkreg_t       ri_part_number            :     16;
		bdrkreg_t       ri_revision               :      4;
		bdrkreg_t       ri_node_id                :      8;
		bdrkreg_t       ri_reserved_1             :      6;
		bdrkreg_t       ri_region_size            :      2;
		bdrkreg_t       ri_reserved               :     16;
	} lb_rev_id_fld_s;
} lb_rev_id_u_t;

#else

typedef union lb_rev_id_u {
        bdrkreg_t       lb_rev_id_regval;
	struct	{
		bdrkreg_t	ri_reserved		  :	16;
		bdrkreg_t	ri_region_size		  :	 2;
		bdrkreg_t	ri_reserved_1		  :	 6;
		bdrkreg_t	ri_node_id		  :	 8;
		bdrkreg_t	ri_revision		  :	 4;
		bdrkreg_t	ri_part_number		  :	16;
		bdrkreg_t	ri_manufacturer		  :	11;
		bdrkreg_t	ri_reserved_2		  :	 1;
	} lb_rev_id_fld_s;
} lb_rev_id_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register contains the PI-access-rights bit-vector for the      *
 * LB, NI, XB and MD portions of the Bedrock local register space. If   *
 * a bit in the bit-vector is set, the region corresponding to that     *
 * bit has read/write permission on the LB, NI, XB and MD local         *
 * registers. If the bit is clear, that region has no write access to   *
 * the local registers and no read access if the read will cause any    *
 * state change. If a write or a read with side effects is attempted    *
 * by a PI in a region for which access is restricted, the LB will      *
 * not perform the operation and will send back a reply which           *
 * indicates an error.                                                  *
 *                                                                      *
 ************************************************************************/




typedef union lb_cpu_permission_u {
	bdrkreg_t	lb_cpu_permission_regval;
	struct  {
		bdrkreg_t	cp_cpu_access             :	64;
	} lb_cpu_permission_fld_s;
} lb_cpu_permission_u_t;




/************************************************************************
 *                                                                      *
 *  A write to this register of the 64-bit value "SGIrules" will        *
 * cause the bit in the LB_CPU_PROTECT register corresponding to the    *
 * region of the requester to be set.                                   *
 *                                                                      *
 ************************************************************************/




typedef union lb_cpu_perm_ovrrd_u {
	bdrkreg_t	lb_cpu_perm_ovrrd_regval;
	struct  {
		bdrkreg_t	cpo_cpu_perm_ovr          :	64;
	} lb_cpu_perm_ovrrd_fld_s;
} lb_cpu_perm_ovrrd_u_t;




/************************************************************************
 *                                                                      *
 *  This register contains the II-access-rights bit-vector for the      *
 * LB, NI, XB and MD portions of the Bedrock local register space. If   *
 * a bit in the bit-vector is set, the region corresponding to that     *
 * bit has read/write permission on the LB, NI, XB and MD local         *
 * registers. If the bit is clear, then that region has no write        *
 * access to the local registers and no read access if the read         *
 * results in any state change. If a write or a read with side          *
 * effects is attempted by an II in a region for which access is        *
 * restricted, the LB will not perform the operation and will send      *
 * back a reply which indicates an error.                               *
 *                                                                      *
 ************************************************************************/




typedef union lb_io_permission_u {
	bdrkreg_t	lb_io_permission_regval;
	struct  {
		bdrkreg_t	ip_io_permission          :	64;
	} lb_io_permission_fld_s;
} lb_io_permission_u_t;




/************************************************************************
 *                                                                      *
 *  A write to this bit resets the Bedrock chip with a soft reset.      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union lb_soft_reset_u {
	bdrkreg_t	lb_soft_reset_regval;
	struct  {
		bdrkreg_t	sr_soft_reset             :	 1;
		bdrkreg_t	sr_reserved		  :	63;
	} lb_soft_reset_fld_s;
} lb_soft_reset_u_t;