hubpi.h

上传linux-jx2410的源代码

	struct  {
		bdrkreg_t	pc_profile_compare        :	32;
		bdrkreg_t       pc_rsvd                   :     32;
	} pi_profile_compare_fld_s;
} pi_profile_compare_u_t;

#else

typedef union pi_profile_compare_u {
	bdrkreg_t	pi_profile_compare_regval;
	struct	{
		bdrkreg_t	pc_rsvd			  :	32;
		bdrkreg_t	pc_profile_compare	  :	32;
	} pi_profile_compare_fld_s;
} pi_profile_compare_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. If the bit in the     *
 * corresponding RT_INT_EN_A/B register is set, the processor's level   *
 * 5 interrupt is set to the value of the RTC_INT_PEND bit in this      *
 * register. Storing any value to this location will clear the          *
 * RTC_INT_PEND bit in the register.                                    *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_int_pend_a_u {
	bdrkreg_t	pi_rt_int_pend_a_regval;
	struct  {
		bdrkreg_t	ripa_rtc_int_pend         :	 1;
		bdrkreg_t       ripa_rsvd                 :     63;
	} pi_rt_int_pend_a_fld_s;
} pi_rt_int_pend_a_u_t;

#else

typedef union pi_rt_int_pend_a_u {
	bdrkreg_t	pi_rt_int_pend_a_regval;
	struct	{
		bdrkreg_t	ripa_rsvd		  :	63;
		bdrkreg_t	ripa_rtc_int_pend	  :	 1;
	} pi_rt_int_pend_a_fld_s;
} pi_rt_int_pend_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. If the bit in the     *
 * corresponding RT_INT_EN_A/B register is set, the processor's level   *
 * 5 interrupt is set to the value of the RTC_INT_PEND bit in this      *
 * register. Storing any value to this location will clear the          *
 * RTC_INT_PEND bit in the register.                                    *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_int_pend_b_u {
	bdrkreg_t	pi_rt_int_pend_b_regval;
	struct  {
		bdrkreg_t	ripb_rtc_int_pend         :	 1;
		bdrkreg_t       ripb_rsvd                 :     63;
	} pi_rt_int_pend_b_fld_s;
} pi_rt_int_pend_b_u_t;

#else

typedef union pi_rt_int_pend_b_u {
	bdrkreg_t	pi_rt_int_pend_b_regval;
	struct	{
		bdrkreg_t	ripb_rsvd		  :	63;
		bdrkreg_t	ripb_rtc_int_pend	  :	 1;
	} pi_rt_int_pend_b_fld_s;
} pi_rt_int_pend_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Both registers are    *
 * set when the PROFILE_COMPARE register is equal to bits [31:0] of     *
 * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B      *
 * register is set, the processor's level 5 interrupt is set to the     *
 * value of the PROF_INT_PEND bit in this register. Storing any value   *
 * to this location will clear the PROF_INT_PEND bit in the register.   *
 * The reason for having A and B versions of this register is that      *
 * they need to be cleared independently.                               *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_prof_int_pend_a_u {
	bdrkreg_t	pi_prof_int_pend_a_regval;
	struct  {
		bdrkreg_t	pipa_prof_int_pend        :	 1;
		bdrkreg_t       pipa_rsvd                 :     63;
	} pi_prof_int_pend_a_fld_s;
} pi_prof_int_pend_a_u_t;

#else

typedef union pi_prof_int_pend_a_u {
	bdrkreg_t	pi_prof_int_pend_a_regval;
	struct	{
		bdrkreg_t	pipa_rsvd		  :	63;
		bdrkreg_t	pipa_prof_int_pend	  :	 1;
	} pi_prof_int_pend_a_fld_s;
} pi_prof_int_pend_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Both registers are    *
 * set when the PROFILE_COMPARE register is equal to bits [31:0] of     *
 * the RT_Counter. If the bit in the corresponding PROF_INT_EN_A/B      *
 * register is set, the processor's level 5 interrupt is set to the     *
 * value of the PROF_INT_PEND bit in this register. Storing any value   *
 * to this location will clear the PROF_INT_PEND bit in the register.   *
 * The reason for having A and B versions of this register is that      *
 * they need to be cleared independently.                               *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_prof_int_pend_b_u {
	bdrkreg_t	pi_prof_int_pend_b_regval;
	struct  {
		bdrkreg_t	pipb_prof_int_pend        :	 1;
		bdrkreg_t       pipb_rsvd                 :     63;
	} pi_prof_int_pend_b_fld_s;
} pi_prof_int_pend_b_u_t;

#else

typedef union pi_prof_int_pend_b_u {
	bdrkreg_t	pi_prof_int_pend_b_regval;
	struct	{
		bdrkreg_t	pipb_rsvd		  :	63;
		bdrkreg_t	pipb_prof_int_pend	  :	 1;
	} pi_prof_int_pend_b_fld_s;
} pi_prof_int_pend_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Enables RTC           *
 * interrupt to the associated CPU.                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_int_en_a_u {
	bdrkreg_t	pi_rt_int_en_a_regval;
	struct  {
		bdrkreg_t	riea_rtc_int_en           :	 1;
		bdrkreg_t       riea_rsvd                 :     63;
	} pi_rt_int_en_a_fld_s;
} pi_rt_int_en_a_u_t;

#else

typedef union pi_rt_int_en_a_u {
        bdrkreg_t       pi_rt_int_en_a_regval;
        struct  {
                bdrkreg_t       riea_rsvd                 :     63;
                bdrkreg_t       riea_rtc_int_en           :      1;
        } pi_rt_int_en_a_fld_s;
} pi_rt_int_en_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Enables RTC           *
 * interrupt to the associated CPU.                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_int_en_b_u {
	bdrkreg_t	pi_rt_int_en_b_regval;
	struct  {
		bdrkreg_t	rieb_rtc_int_en           :	 1;
		bdrkreg_t       rieb_rsvd                 :     63;
	} pi_rt_int_en_b_fld_s;
} pi_rt_int_en_b_u_t;

#else

typedef union pi_rt_int_en_b_u {
        bdrkreg_t       pi_rt_int_en_b_regval;
        struct  {
                bdrkreg_t       rieb_rsvd                 :     63;
                bdrkreg_t       rieb_rtc_int_en           :      1;
        } pi_rt_int_en_b_fld_s;
} pi_rt_int_en_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Enables profiling     *
 * interrupt to the associated CPU.                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_prof_int_en_a_u {
	bdrkreg_t	pi_prof_int_en_a_regval;
	struct  {
		bdrkreg_t	piea_prof_int_en          :	 1;
		bdrkreg_t       piea_rsvd                 :     63;
	} pi_prof_int_en_a_fld_s;
} pi_prof_int_en_a_u_t;

#else

typedef union pi_prof_int_en_a_u {
	bdrkreg_t	pi_prof_int_en_a_regval;
	struct	{
		bdrkreg_t	piea_rsvd		  :	63;
		bdrkreg_t	piea_prof_int_en	  :	 1;
	} pi_prof_int_en_a_fld_s;
} pi_prof_int_en_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Enables profiling     *
 * interrupt to the associated CPU.                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_prof_int_en_b_u {
	bdrkreg_t	pi_prof_int_en_b_regval;
	struct  {
		bdrkreg_t	pieb_prof_int_en          :	 1;
		bdrkreg_t       pieb_rsvd                 :     63;
	} pi_prof_int_en_b_fld_s;
} pi_prof_int_en_b_u_t;

#else

typedef union pi_prof_int_en_b_u {
	bdrkreg_t	pi_prof_int_en_b_regval;
	struct	{
		bdrkreg_t	pieb_rsvd		  :	63;
		bdrkreg_t	pieb_prof_int_en	  :	 1;
	} pi_prof_int_en_b_fld_s;
} pi_prof_int_en_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register controls operation of the debug data from the PI,     *
 * along with Debug_Sel[2:0] from the Debug module. For some values     *
 * of Debug_Sel[2:0], the B_SEL bit selects whether the debug bits      *
 * are looking at the processor A or processor B logic. The remaining   *
 * bits select which signal(s) are ORed to create DebugData bits 31     *
 * and 30 for all of the PI debug selections.                           *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_debug_sel_u {
	bdrkreg_t	pi_debug_sel_regval;
	struct  {
		bdrkreg_t	ds_low_t5cc_a             :	 1;
                bdrkreg_t       ds_low_t5cc_b             :      1;
                bdrkreg_t       ds_low_totcc_a            :      1;
                bdrkreg_t       ds_low_totcc_b            :      1;
                bdrkreg_t       ds_low_reqcc_a            :      1;
                bdrkreg_t       ds_low_reqcc_b            :      1;
                bdrkreg_t       ds_low_rplcc_a            :      1;
                bdrkreg_t       ds_low_rplcc_b            :      1;
                bdrkreg_t       ds_low_intcc              :      1;
                bdrkreg_t       ds_low_perf_inc_a_0       :      1;
                bdrkreg_t       ds_low_perf_inc_a_1       :      1;
                bdrkreg_t       ds_low_perf_inc_b_0       :      1;
                bdrkreg_t       ds_low_perf_inc_b_1       :      1;
                bdrkreg_t       ds_high_t5cc_a            :      1;
                bdrkreg_t       ds_high_t5cc_b            :      1;
                bdrkreg_t       ds_high_totcc_a           :      1;
                bdrkreg_t       ds_high_totcc_b           :      1;
                bdrkreg_t       ds_high_reqcc_a           :      1;
                bdrkreg_t       ds_high_reqcc_b           :      1;
                bdrkreg_t       ds_high_rplcc_a           :      1;
                bdrkreg_t       ds_high_rplcc_b           :      1;
                bdrkreg_t       ds_high_intcc             :      1;
                bdrkreg_t       ds_high_perf_inc_a_0      :      1;
                bdrkreg_t       ds_high_perf_inc_a_1      :      1;
                bdrkreg_t       ds_high_perf_inc_b_0      :      1;
                bdrkreg_t       ds_high_perf_inc_b_1      :      1;
                bdrkreg_t       ds_b_sel                  :      1;
                bdrkreg_t       ds_rsvd                   :     37;
	} pi_debug_sel_fld_s;
} pi_debug_sel_u_t;

#else

typedef union pi_debug_sel_u {
	bdrkreg_t	pi_debug_sel_regval;
	struct	{
		bdrkreg_t	ds_rsvd			  :	37;
		bdrkreg_t	ds_b_sel		  :	 1;
		bdrkreg_t	ds_high_perf_inc_b_1	  :	 1;
		bdrkreg_t	ds_high_perf_inc_b_0	  :	 1;
		bdrkreg_t	ds_high_perf_inc_a_1	  :	 1;
		bdrkreg_t	ds_high_perf_inc_a_0	  :	 1;
		bdrkreg_t	ds_high_intcc		  :	 1;
		bdrkreg_t	ds_high_rplcc_b		  :	 1;
		bdrkreg_t	ds_high_rplcc_a		  :	 1;
		bdrkreg_t	ds_high_reqcc_b		  :	 1;
		bdrkreg_t	ds_high_reqcc_a		  :	 1;
		bdrkreg_t	ds_high_totcc_b		  :	 1;
		bdrkreg_t	ds_high_totcc_a		  :	 1;
		bdrkreg_t	ds_high_t5cc_b		  :	 1;