hubpi.h

上传linux-jx2410的源代码

typedef union pi_int_mask0_a_u {
	bdrkreg_t	pi_int_mask0_a_regval;
	struct  {
		bdrkreg_t	ima_int_mask0_lo          :	 1;
                bdrkreg_t       ima_gfx_int_a             :      1;
                bdrkreg_t       ima_gfx_int_b             :      1;
                bdrkreg_t       ima_page_migration        :      1;
                bdrkreg_t       ima_uart_ucntrl           :      1;
                bdrkreg_t       ima_or_ccp_mask_a         :      1;
                bdrkreg_t       ima_or_ccp_mask_b         :      1;
                bdrkreg_t       ima_int_mask0_hi          :     57;
	} pi_int_mask0_a_fld_s;
} pi_int_mask0_a_u_t;

#else

typedef union pi_int_mask0_a_u {
	bdrkreg_t	pi_int_mask0_a_regval;
	struct	{
		bdrkreg_t	ima_int_mask0_hi	  :	57;
		bdrkreg_t	ima_or_ccp_mask_b	  :	 1;
		bdrkreg_t	ima_or_ccp_mask_a	  :	 1;
		bdrkreg_t	ima_uart_ucntrl		  :	 1;
		bdrkreg_t	ima_page_migration	  :	 1;
		bdrkreg_t	ima_gfx_int_b		  :	 1;
		bdrkreg_t	ima_gfx_int_a		  :	 1;
		bdrkreg_t	ima_int_mask0_lo	  :	 1;
	} pi_int_mask0_a_fld_s;
} pi_int_mask0_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This read/write register masks the contents of INT_PEND1 to         *
 * determine whether an interrupt should be sent. Bits 63:32 always     *
 * generate an L3 interrupt (bit 11 of the processor's Cause            *
 * register) is sent to CPU_A if the same bit in the INT_PEND1          *
 * register is set. Bits 31:0 can generate either an L3 or L2           *
 * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only      *
 * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR,     *
 * XB_ERROR and MD_CORR_ERROR bits.                                     *
 *                                                                      *
 ************************************************************************/




typedef union pi_int_mask1_a_u {
	bdrkreg_t	pi_int_mask1_a_regval;
	struct  {
		bdrkreg_t	ima_int_mask1             :	64;
	} pi_int_mask1_a_fld_s;
} pi_int_mask1_a_u_t;




/************************************************************************
 *                                                                      *
 *  This read/write register masks the contents of INT_PEND0 to         *
 * determine whether an L2 interrupt (bit 10 of the processor's Cause   *
 * register) is sent to CPU_B if the same bit in the INT_PEND0          *
 * register is also set. Only one processor in a Bedrock should         *
 * enable the PAGE_MIGRATION bit/interrupt.                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_int_mask0_b_u {
	bdrkreg_t	pi_int_mask0_b_regval;
	struct  {
		bdrkreg_t	imb_int_mask0_lo          :	 1;
                bdrkreg_t       imb_gfx_int_a             :      1;
                bdrkreg_t       imb_gfx_int_b             :      1;
                bdrkreg_t       imb_page_migration        :      1;
                bdrkreg_t       imb_uart_ucntrl           :      1;
                bdrkreg_t       imb_or_ccp_mask_a         :      1;
                bdrkreg_t       imb_or_ccp_mask_b         :      1;
                bdrkreg_t       imb_int_mask0_hi          :     57;
	} pi_int_mask0_b_fld_s;
} pi_int_mask0_b_u_t;

#else

typedef union pi_int_mask0_b_u {
	bdrkreg_t	pi_int_mask0_b_regval;
	struct	{
		bdrkreg_t	imb_int_mask0_hi	  :	57;
		bdrkreg_t	imb_or_ccp_mask_b	  :	 1;
		bdrkreg_t	imb_or_ccp_mask_a	  :	 1;
		bdrkreg_t	imb_uart_ucntrl		  :	 1;
		bdrkreg_t	imb_page_migration	  :	 1;
		bdrkreg_t	imb_gfx_int_b		  :	 1;
		bdrkreg_t	imb_gfx_int_a		  :	 1;
		bdrkreg_t	imb_int_mask0_lo	  :	 1;
	} pi_int_mask0_b_fld_s;
} pi_int_mask0_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This read/write register masks the contents of INT_PEND1 to         *
 * determine whether an interrupt should be sent. Bits 63:32 always     *
 * generate an L3 interrupt (bit 11 of the processor's Cause            *
 * register) is sent to CPU_B if the same bit in the INT_PEND1          *
 * register is set. Bits 31:0 can generate either an L3 or L2           *
 * interrupt, depending on the value of INT_PEND1_REMAP[3:0]. Only      *
 * one processor in a Bedrock should enable the NI_ERROR, LB_ERROR,     *
 * XB_ERROR and MD_CORR_ERROR bits.                                     *
 *                                                                      *
 ************************************************************************/




typedef union pi_int_mask1_b_u {
	bdrkreg_t	pi_int_mask1_b_regval;
	struct  {
		bdrkreg_t	imb_int_mask1             :	64;
	} pi_int_mask1_b_fld_s;
} pi_int_mask1_b_u_t;




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. These registers do    *
 * not have access protection. A store to this location by a CPU will   *
 * cause the bit corresponding to the source's region to be set in      *
 * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B)   *
 * determines on a bit-per-region basis whether a CPU-to-CPU            *
 * interrupt is pending CPU_A (or CPU_B).                               *
 *                                                                      *
 ************************************************************************/




typedef union pi_cc_pend_set_a_u {
	bdrkreg_t	pi_cc_pend_set_a_regval;
	struct  {
		bdrkreg_t	cpsa_cc_pend              :	64;
	} pi_cc_pend_set_a_fld_s;
} pi_cc_pend_set_a_u_t;




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. These registers do    *
 * not have access protection. A store to this location by a CPU will   *
 * cause the bit corresponding to the source's region to be set in      *
 * CC_PEND_A (or CC_PEND_B). The contents of CC_PEND_A (or CC_PEND_B)   *
 * determines on a bit-per-region basis whether a CPU-to-CPU            *
 * interrupt is pending CPU_A (or CPU_B).                               *
 *                                                                      *
 ************************************************************************/




typedef union pi_cc_pend_set_b_u {
	bdrkreg_t	pi_cc_pend_set_b_regval;
	struct  {
		bdrkreg_t	cpsb_cc_pend              :	64;
	} pi_cc_pend_set_b_fld_s;
} pi_cc_pend_set_b_u_t;




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Reading this          *
 * location will return the contents of CC_PEND_A (or CC_PEND_B).       *
 * Writing this location will clear the bits corresponding to which     *
 * data bits are driven high during the store; therefore, storing all   *
 * ones would clear all bits.                                           *
 *                                                                      *
 ************************************************************************/




typedef union pi_cc_pend_clr_a_u {
	bdrkreg_t	pi_cc_pend_clr_a_regval;
	struct  {
		bdrkreg_t	cpca_cc_pend              :	64;
	} pi_cc_pend_clr_a_fld_s;
} pi_cc_pend_clr_a_u_t;




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. Reading this          *
 * location will return the contents of CC_PEND_A (or CC_PEND_B).       *
 * Writing this location will clear the bits corresponding to which     *
 * data bits are driven high during the store; therefore, storing all   *
 * ones would clear all bits.                                           *
 *                                                                      *
 ************************************************************************/




typedef union pi_cc_pend_clr_b_u {
	bdrkreg_t	pi_cc_pend_clr_b_regval;
	struct  {
		bdrkreg_t	cpcb_cc_pend              :	64;
	} pi_cc_pend_clr_b_fld_s;
} pi_cc_pend_clr_b_u_t;




/************************************************************************
 *                                                                      *
 *  This read/write register masks the contents of both CC_PEND_A and   *
 * CC_PEND_B.                                                           *
 *                                                                      *
 ************************************************************************/




typedef union pi_cc_mask_u {
	bdrkreg_t	pi_cc_mask_regval;
	struct  {
		bdrkreg_t	cm_cc_mask                :	64;
	} pi_cc_mask_fld_s;
} pi_cc_mask_u_t;




/************************************************************************
 *                                                                      *
 *  This read/write register redirects INT_PEND1[31:0] from L3 to L2    *
 * interrupt level.Bit 4 in this register is used to enable error       *
 * interrupt forwarding to the II. When this bit is set, if any of      *
 * the three memory interrupts (correctable error, uncorrectable        *
 * error, or page migration), or the NI, LB or XB error interrupts      *
 * are set, the PI_II_ERROR_INT wire will be asserted. When this wire   *
 * is asserted, the II will send an interrupt to the node specified     *
 * in its IIDSR (Interrupt Destination Register). This allows these     *
 * interrupts to be forwarded to another node.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_int_pend1_remap_u {
	bdrkreg_t	pi_int_pend1_remap_regval;
	struct  {
		bdrkreg_t	ipr_remap_0               :	 1;
                bdrkreg_t       ipr_remap_1               :      1;
                bdrkreg_t       ipr_remap_2               :      1;
                bdrkreg_t       ipr_remap_3               :      1;
                bdrkreg_t       ipr_error_forward         :      1;
                bdrkreg_t       ipr_reserved              :     59;
	} pi_int_pend1_remap_fld_s;
} pi_int_pend1_remap_u_t;

#else

typedef union pi_int_pend1_remap_u {
	bdrkreg_t	pi_int_pend1_remap_regval;
	struct	{
		bdrkreg_t	ipr_reserved		  :	59;
		bdrkreg_t	ipr_error_forward	  :	 1;
		bdrkreg_t	ipr_remap_3		  :	 1;
		bdrkreg_t	ipr_remap_2		  :	 1;
		bdrkreg_t	ipr_remap_1		  :	 1;
		bdrkreg_t	ipr_remap_0		  :	 1;
	} pi_int_pend1_remap_fld_s;
} pi_int_pend1_remap_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. When the real time    *
 * counter (RT_Counter) is equal to the value in this register, the     *
 * RT_INT_PEND register is set, which causes a Level-4 interrupt to     *
 * be sent to the processor.                                            *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_compare_a_u {
	bdrkreg_t	pi_rt_compare_a_regval;
	struct  {
		bdrkreg_t	rca_rt_compare            :	55;
		bdrkreg_t       rca_rsvd                  :      9;
	} pi_rt_compare_a_fld_s;
} pi_rt_compare_a_u_t;

#else

typedef union pi_rt_compare_a_u {
        bdrkreg_t       pi_rt_compare_a_regval;
        struct  {
                bdrkreg_t       rca_rsvd                  :      9;
                bdrkreg_t       rca_rt_compare            :     55;
        } pi_rt_compare_a_fld_s;
} pi_rt_compare_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. When the real time    *
 * counter (RT_Counter) is equal to the value in this register, the     *
 * RT_INT_PEND register is set, which causes a Level-4 interrupt to     *
 * be sent to the processor.                                            *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_rt_compare_b_u {
	bdrkreg_t	pi_rt_compare_b_regval;
	struct  {
		bdrkreg_t	rcb_rt_compare            :	55;
		bdrkreg_t       rcb_rsvd                  :      9;
	} pi_rt_compare_b_fld_s;
} pi_rt_compare_b_u_t;

#else

typedef union pi_rt_compare_b_u {
	bdrkreg_t	pi_rt_compare_b_regval;
	struct	{
		bdrkreg_t	rcb_rsvd		  :	 9;
		bdrkreg_t	rcb_rt_compare		  :	55;
	} pi_rt_compare_b_fld_s;
} pi_rt_compare_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  When the least significant 32 bits of the real time counter         *
 * (RT_Counter) are equal to the value in this register, the            *
 * PROF_INT_PEND_A and PROF_INT_PEND_B registers are set to 0x1.        *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_profile_compare_u {
	bdrkreg_t	pi_profile_compare_regval;