hubpi.h

上传linux-jx2410的源代码

#ifdef LITTLE_ENDIAN

typedef union pi_crb_sfactor_u {
	bdrkreg_t	pi_crb_sfactor_regval;
	struct  {
		bdrkreg_t	cs_sfactor                :	24;
		bdrkreg_t       cs_rsvd                   :     40;
	} pi_crb_sfactor_fld_s;
} pi_crb_sfactor_u_t;

#else

typedef union pi_crb_sfactor_u {
	bdrkreg_t	pi_crb_sfactor_regval;
	struct	{
		bdrkreg_t	cs_rsvd			  :	40;
		bdrkreg_t	cs_sfactor		  :	24;
	} pi_crb_sfactor_fld_s;
} pi_crb_sfactor_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. The PI sets this      *
 * bit when it sees the first transaction initiated by the associated   *
 * CPU.                                                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_cpu_present_a_u {
	bdrkreg_t	pi_cpu_present_a_regval;
	struct  {
		bdrkreg_t	cpa_cpu_present           :	 1;
		bdrkreg_t       cpa_rsvd                  :     63;
	} pi_cpu_present_a_fld_s;
} pi_cpu_present_a_u_t;

#else

typedef union pi_cpu_present_a_u {
	bdrkreg_t	pi_cpu_present_a_regval;
	struct	{
		bdrkreg_t	cpa_rsvd		  :	63;
		bdrkreg_t	cpa_cpu_present		  :	 1;
	} pi_cpu_present_a_fld_s;
} pi_cpu_present_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. The PI sets this      *
 * bit when it sees the first transaction initiated by the associated   *
 * CPU.                                                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_cpu_present_b_u {
	bdrkreg_t	pi_cpu_present_b_regval;
	struct  {
		bdrkreg_t	cpb_cpu_present           :	 1;
		bdrkreg_t       cpb_rsvd                  :     63;
	} pi_cpu_present_b_fld_s;
} pi_cpu_present_b_u_t;

#else

typedef union pi_cpu_present_b_u {
	bdrkreg_t	pi_cpu_present_b_regval;
	struct	{
		bdrkreg_t	cpb_rsvd		  :	63;
		bdrkreg_t	cpb_cpu_present		  :	 1;
	} pi_cpu_present_b_fld_s;
} pi_cpu_present_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  There is one of these registers for each CPU. This     *
 * Read/Write location determines whether the associated CPU is         *
 * enabled to issue external requests. When this bit is zero for a      *
 * processor, the PI ignores SysReq_L from that processor, and so       *
 * never grants it the bus.                                             *
 * This register is not reset by a soft reset.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_cpu_enable_a_u {
	bdrkreg_t	pi_cpu_enable_a_regval;
	struct  {
		bdrkreg_t	cea_cpu_enable            :	 1;
		bdrkreg_t       cea_rsvd                  :     63;
	} pi_cpu_enable_a_fld_s;
} pi_cpu_enable_a_u_t;

#else

typedef union pi_cpu_enable_a_u {
	bdrkreg_t	pi_cpu_enable_a_regval;
	struct	{
		bdrkreg_t	cea_rsvd		  :	63;
		bdrkreg_t	cea_cpu_enable		  :	 1;
	} pi_cpu_enable_a_fld_s;
} pi_cpu_enable_a_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  There is one of these registers for each CPU. This     *
 * Read/Write location determines whether the associated CPU is         *
 * enabled to issue external requests. When this bit is zero for a      *
 * processor, the PI ignores SysReq_L from that processor, and so       *
 * never grants it the bus.                                             *
 * This register is not reset by a soft reset.                          *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_cpu_enable_b_u {
	bdrkreg_t	pi_cpu_enable_b_regval;
	struct  {
		bdrkreg_t	ceb_cpu_enable            :	 1;
		bdrkreg_t       ceb_rsvd                  :     63;
	} pi_cpu_enable_b_fld_s;
} pi_cpu_enable_b_u_t;

#else

typedef union pi_cpu_enable_b_u {
	bdrkreg_t	pi_cpu_enable_b_regval;
	struct	{
		bdrkreg_t	ceb_rsvd		  :	63;
		bdrkreg_t	ceb_cpu_enable		  :	 1;
	} pi_cpu_enable_b_fld_s;
} pi_cpu_enable_b_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. A write to this       *
 * location will cause an NMI to be issued to the CPU.                  *
 *                                                                      *
 ************************************************************************/




typedef union pi_nmi_a_u {
	bdrkreg_t	pi_nmi_a_regval;
	struct  {
		bdrkreg_t	na_nmi_cpu                :	64;
	} pi_nmi_a_fld_s;
} pi_nmi_a_u_t;




/************************************************************************
 *                                                                      *
 *  There is one of these registers for each CPU. A write to this       *
 * location will cause an NMI to be issued to the CPU.                  *
 *                                                                      *
 ************************************************************************/




typedef union pi_nmi_b_u {
	bdrkreg_t	pi_nmi_b_regval;
	struct  {
		bdrkreg_t	nb_nmi_cpu                :	64;
	} pi_nmi_b_fld_s;
} pi_nmi_b_u_t;




/************************************************************************
 *                                                                      *
 *  A write to this register allows a single bit in the INT_PEND0 or    *
 * INT_PEND1 registers to be set or cleared. If 6 is clear, a bit is    *
 * modified in INT_PEND0, while if 6 is set, a bit is modified in       *
 * INT_PEND1. The value in 5:0 (ranging from 63 to 0) will determine    *
 * which bit in the register is effected. The value of 8 will           *
 * determine whether the desired bit is set (8=1) or cleared (8=0).     *
 * This is the only register which is accessible by IO issued PWRI      *
 * command and is protected through the IO_PROTECT register. If the     *
 * region bit in the IO_PROTECT is not set then a WERR reply is         *
 * issued. CPU access is controlled through CPU_PROTECT. The contents   *
 * of this register are masked with the contents of INT_MASK_A          *
 * (INT_MASK_B) to determine whether an L2 interrupt is issued to       *
 * CPU_A (CPU_B).                                                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_int_pend_mod_u {
	bdrkreg_t	pi_int_pend_mod_regval;
	struct  {
		bdrkreg_t	ipm_bit_select            :	 6;
                bdrkreg_t       ipm_reg_select            :      1;
                bdrkreg_t       ipm_rsvd_1                :      1;
                bdrkreg_t       ipm_value                 :      1;
                bdrkreg_t       ipm_rsvd                  :     55;
	} pi_int_pend_mod_fld_s;
} pi_int_pend_mod_u_t;

#else

typedef union pi_int_pend_mod_u {
	bdrkreg_t	pi_int_pend_mod_regval;
	struct	{
		bdrkreg_t	ipm_rsvd		  :	55;
		bdrkreg_t	ipm_value		  :	 1;
		bdrkreg_t	ipm_rsvd_1		  :	 1;
		bdrkreg_t	ipm_reg_select		  :	 1;
		bdrkreg_t	ipm_bit_select		  :	 6;
	} pi_int_pend_mod_fld_s;
} pi_int_pend_mod_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This read-only register provides information about interrupts       *
 * that are currently pending. The interrupts in this register map to   *
 * interrupt level 2 (L2). The GFX_INT_A/B bits are set by hardware     *
 * but must be cleared by software.                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_int_pend0_u {
	bdrkreg_t	pi_int_pend0_regval;
	struct  {
		bdrkreg_t	ip_int_pend0_lo           :	 1;
                bdrkreg_t       ip_gfx_int_a              :      1;
                bdrkreg_t       ip_gfx_int_b              :      1;
                bdrkreg_t       ip_page_migration         :      1;
                bdrkreg_t       ip_uart_ucntrl            :      1;
                bdrkreg_t       ip_or_cc_pend_a           :      1;
                bdrkreg_t       ip_or_cc_pend_b           :      1;
                bdrkreg_t       ip_int_pend0_hi           :     57;
	} pi_int_pend0_fld_s;
} pi_int_pend0_u_t;

#else

typedef union pi_int_pend0_u {
	bdrkreg_t	pi_int_pend0_regval;
	struct	{
		bdrkreg_t	ip_int_pend0_hi		  :	57;
		bdrkreg_t	ip_or_cc_pend_b		  :	 1;
		bdrkreg_t	ip_or_cc_pend_a		  :	 1;
		bdrkreg_t	ip_uart_ucntrl		  :	 1;
		bdrkreg_t	ip_page_migration	  :	 1;
		bdrkreg_t	ip_gfx_int_b		  :	 1;
		bdrkreg_t	ip_gfx_int_a		  :	 1;
		bdrkreg_t	ip_int_pend0_lo		  :	 1;
	} pi_int_pend0_fld_s;
} pi_int_pend0_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This read-only register provides information about interrupts       *
 * that are currently pending. The interrupts in this register map to   *
 * interrupt level 3 (L3), unless remapped by the INT_PEND1_REMAP       *
 * register. The SYS_COR_ERR_A/B, RTC_DROP_OUT, and NACK_INT_A/B bits   *
 * are set by hardware but must be cleared by software. The             *
 * SYSTEM_SHUTDOWN, NI_ERROR, LB_ERROR and XB_ERROR bits just reflect   *
 * the value of other logic, and cannot be changed by PI register       *
 * writes.                                                              *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_int_pend1_u {
	bdrkreg_t	pi_int_pend1_regval;
	struct  {
		bdrkreg_t	ip_int_pend1              :	54;
                bdrkreg_t       ip_xb_error               :      1;
                bdrkreg_t       ip_lb_error               :      1;
                bdrkreg_t       ip_nack_int_a             :      1;
                bdrkreg_t       ip_nack_int_b             :      1;
                bdrkreg_t       ip_perf_cntr_oflow        :      1;
                bdrkreg_t       ip_sys_cor_err_b          :      1;
                bdrkreg_t       ip_sys_cor_err_a          :      1;
                bdrkreg_t       ip_md_corr_error          :      1;
                bdrkreg_t       ip_ni_error               :      1;
                bdrkreg_t       ip_system_shutdown        :      1;
	} pi_int_pend1_fld_s;
} pi_int_pend1_u_t;

#else

typedef union pi_int_pend1_u {
	bdrkreg_t	pi_int_pend1_regval;
	struct	{
		bdrkreg_t	ip_system_shutdown	  :	 1;
		bdrkreg_t	ip_ni_error		  :	 1;
		bdrkreg_t	ip_md_corr_error	  :	 1;
		bdrkreg_t	ip_sys_cor_err_a	  :	 1;
		bdrkreg_t	ip_sys_cor_err_b	  :	 1;
		bdrkreg_t	ip_perf_cntr_oflow	  :	 1;
		bdrkreg_t	ip_nack_int_b		  :	 1;
		bdrkreg_t	ip_nack_int_a		  :	 1;
		bdrkreg_t	ip_lb_error		  :	 1;
		bdrkreg_t	ip_xb_error		  :	 1;
		bdrkreg_t	ip_int_pend1		  :	54;
	} pi_int_pend1_fld_s;
} pi_int_pend1_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This read/write register masks the contents of INT_PEND0 to         *
 * determine whether an L2 interrupt (bit 10 of the processor's Cause   *
 * register) is sent to CPU_A if the same bit in the INT_PEND0          *
 * register is also set. Only one processor in a Bedrock should         *
 * enable the PAGE_MIGRATION bit/interrupt.                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN