hubpi.h

上传linux-jx2410的源代码

                                                    * Error Interrupt
                                                    * Pending (Writable)
                                                    */



#define    PI_ERR_INT_PEND           0x00000400    /*
                                                    * Error Interrupt
                                                    * Pending
                                                    */



#define    PI_ERR_INT_MASK_A         0x00000408    /*
                                                    * Error Interrupt
                                                    * Mask CPU_A
                                                    */



#define    PI_ERR_INT_MASK_B         0x00000410    /*
                                                    * Error Interrupt
                                                    * Mask CPU_B
                                                    */



#define    PI_ERR_STACK_ADDR_A       0x00000418    /*
                                                    * Error Stack Address
                                                    * Pointer
                                                    */



#define    PI_ERR_STACK_ADDR_B       0x00000420    /*
                                                    * Error Stack Address
                                                    * Pointer
                                                    */



#define    PI_ERR_STACK_SIZE         0x00000428    /* Error Stack Size       */



#define    PI_ERR_STATUS0_A          0x00000430    /* Error Status 0         */



#define    PI_ERR_STATUS0_A_CLR      0x00000438    /* Error Status 0         */



#define    PI_ERR_STATUS1_A          0x00000440    /* Error Status 1         */



#define    PI_ERR_STATUS1_A_CLR      0x00000448    /* Error Status 1         */



#define    PI_ERR_STATUS0_B          0x00000450    /* Error Status 0         */



#define    PI_ERR_STATUS0_B_CLR      0x00000458    /* Error Status 0         */



#define    PI_ERR_STATUS1_B          0x00000460    /* Error Status 1         */



#define    PI_ERR_STATUS1_B_CLR      0x00000468    /* Error Status 1         */



#define    PI_SPOOL_CMP_A            0x00000470    /* Spool Compare          */



#define    PI_SPOOL_CMP_B            0x00000478    /* Spool Compare          */



#define    PI_CRB_TIMEOUT_A          0x00000480    /*
                                                    * CRB entries which
                                                    * have timed out but
                                                    * are still valid
                                                    */



#define    PI_CRB_TIMEOUT_B          0x00000488    /*
                                                    * CRB entries which
                                                    * have timed out but
                                                    * are still valid
                                                    */



#define    PI_SYSAD_ERRCHK_EN        0x00000490    /*
                                                    * enables
                                                    * sysad/cmd/state
                                                    * error checking
                                                    */



#define    PI_FORCE_BAD_CHECK_BIT_A  0x00000498    /*
                                                    * force SysAD Check
                                                    * Bit error
                                                    */



#define    PI_FORCE_BAD_CHECK_BIT_B  0x000004A0    /*
                                                    * force SysAD Check
                                                    * Bit error
                                                    */



#define    PI_NACK_CNT_A             0x000004A8    /*
                                                    * consecutive NACK
                                                    * counter
                                                    */



#define    PI_NACK_CNT_B             0x000004B0    /*
                                                    * consecutive NACK
                                                    * counter
                                                    */



#define    PI_NACK_CMP               0x000004B8    /* NACK count compare     */



#define    PI_SPOOL_MASK             0x000004C0    /* Spool error mask       */



#define    PI_SPURIOUS_HDR_0         0x000004C8    /* Spurious Error 0       */



#define    PI_SPURIOUS_HDR_1         0x000004D0    /* Spurious Error 1       */



#define    PI_ERR_INJECT             0x000004D8    /*
                                                    * SysAD bus error
                                                    * injection
                                                    */





#ifdef _LANGUAGE_C

/************************************************************************
 *                                                                      *
 * Description:  This read/write register determines on a               *
 * bit-per-region basis whether incoming CPU-initiated PIO Read and     *
 * Write to local PI registers are allowed. If access is allowed, the   *
 * PI's response to a partial read is a PRPLY message, and the          *
 * response to a partial write is a PACK message. If access is not      *
 * allowed, the PI's response to a partial read is a PRERR message,     *
 * and the response to a partial write is a PWERR message.              *
 * This register is not reset by a soft reset.                          *
 *                                                                      *
 ************************************************************************/




typedef union pi_cpu_protect_u {
	bdrkreg_t	pi_cpu_protect_regval;
	struct  {
		bdrkreg_t	cp_cpu_protect            :	64;
	} pi_cpu_protect_fld_s;
} pi_cpu_protect_u_t;




/************************************************************************
 *                                                                      *
 *  A write with a special data pattern allows any CPU to set its       *
 * region's bit in CPU_PROTECT. This register has data pattern          *
 * protection.                                                          *
 *                                                                      *
 ************************************************************************/




typedef union pi_prot_ovrrd_u {
	bdrkreg_t	pi_prot_ovrrd_regval;
	struct  {
		bdrkreg_t	po_prot_ovrrd             :	64;
	} pi_prot_ovrrd_fld_s;
} pi_prot_ovrrd_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This read/write register determines on a               *
 * bit-per-region basis whether incoming IO-initiated interrupts are    *
 * allowed to set bits in INT_PEND0 and INT_PEND1. If access is         *
 * allowed, the PI's response to a partial read is a PRPLY message,     *
 * and the response to a partial write is a PACK message. If access     *
 * is not allowed, the PI's response to a partial read is a PRERR       *
 * message, and the response to a partial write is a PWERR message.     *
 * This register is not reset by a soft reset.                          *
 *                                                                      *
 ************************************************************************/




typedef union pi_io_protect_u {
	bdrkreg_t	pi_io_protect_regval;
	struct  {
		bdrkreg_t	ip_io_protect             :	64;
	} pi_io_protect_fld_s;
} pi_io_protect_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This read/write register determines on a               *
 * bit-per-region basis whether read access from a local processor to   *
 * the region is permissible. For example, setting a bit to 0           *
 * prevents speculative reads to that non-existent node. If a read      *
 * request to a non-present region occurs, an ERR response is issued    *
 * to the TRex+ (no PI error registers are modified). It is up to       *
 * software to load this register with the proper contents.             *
 * Region-present checking is only done for coherent read requests -    *
 * partial reads/writes will be issued to a non-present region. The     *
 * setting of these bits does not affect a node's access to its         *
 * CALIAS space.                                                        *
 * This register is not reset by a soft reset.                          *
 *                                                                      *
 ************************************************************************/




typedef union pi_region_present_u {
	bdrkreg_t	pi_region_present_regval;
	struct  {
		bdrkreg_t	rp_region_present         :	64;
	} pi_region_present_fld_s;
} pi_region_present_u_t;




/************************************************************************
 *                                                                      *
 *  A read to the location will allow a CPU to identify itself as       *
 * either CPU_A or CPU_B, and will indicate whether the CPU is          *
 * connected to PI 0 or PI 1.                                           *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_cpu_num_u {
	bdrkreg_t	pi_cpu_num_regval;
	struct  {
		bdrkreg_t	cn_cpu_num                :	 1;
                bdrkreg_t       cn_pi_id                  :      1;
                bdrkreg_t       cn_rsvd                   :     62;
	} pi_cpu_num_fld_s;
} pi_cpu_num_u_t;

#else

typedef union pi_cpu_num_u {
	bdrkreg_t	pi_cpu_num_regval;
	struct	{
		bdrkreg_t	cn_rsvd			  :	62;
		bdrkreg_t	cn_pi_id		  :	 1;
		bdrkreg_t	cn_cpu_num		  :	 1;
	} pi_cpu_num_fld_s;
} pi_cpu_num_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This read/write location determines the size of the    *
 * Calias Space.                                                        *
 * This register is not reset by a soft reset.                          *
 * NOTE: For predictable behavior, all Calias spaces in a system must   *
 * be set to the same size.                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_calias_size_u {
	bdrkreg_t	pi_calias_size_regval;
	struct  {
		bdrkreg_t	cs_calias_size            :	 4;
		bdrkreg_t       cs_rsvd                   :     60;
	} pi_calias_size_fld_s;
} pi_calias_size_u_t;

#else

typedef union pi_calias_size_u {
	bdrkreg_t	pi_calias_size_regval;
	struct	{
		bdrkreg_t	cs_rsvd			  :	60;
		bdrkreg_t	cs_calias_size		  :	 4;
	} pi_calias_size_fld_s;
} pi_calias_size_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This Read/Write location determines at which value (increment)      *
 * the CRB Timeout Counters cause a timeout error to occur. See         *
 * Section 3.4.2.2, "Time-outs in RRB and WRB" in the         *
 * Processor Interface chapter, volume 1 of this document for more      *
 * details.                                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union pi_max_crb_timeout_u {
	bdrkreg_t	pi_max_crb_timeout_regval;
	struct  {
		bdrkreg_t	mct_max_timeout           :	 8;
		bdrkreg_t       mct_rsvd                  :     56;
	} pi_max_crb_timeout_fld_s;
} pi_max_crb_timeout_u_t;

#else

typedef union pi_max_crb_timeout_u {
	bdrkreg_t	pi_max_crb_timeout_regval;
	struct	{
		bdrkreg_t	mct_rsvd		  :	56;
		bdrkreg_t	mct_max_timeout		  :	 8;
	} pi_max_crb_timeout_fld_s;
} pi_max_crb_timeout_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This Read/Write location determines how often a valid CRB's         *
 * Timeout Counter is incremented. See Section 3.4.2.2,                 *
 * "Time-outs in RRB and WRB" in the Processor Interface      *
 * chapter, volume 1 of this document for more details.                 *
 *                                                                      *
 ************************************************************************/