hubpi.h

上传linux-jx2410的源代码

/* $Id: hubpi.h,v 1.1.1.1 2004/02/04 12:57:43 laputa Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2000 by Colin Ngam
 */
#ifndef _ASM_SN_SN1_HUBPI_H
#define _ASM_SN_SN1_HUBPI_H

/************************************************************************
 *                                                                      *
 *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
 *                                                                      *
 * This file is created by an automated script. Any (minimal) changes   *
 * made manually to this  file should be made with care.                *
 *                                                                      *
 *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
 *                                                                      *
 ************************************************************************/


#define    PI_CPU_PROTECT            0x00000000    /* CPU Protection         */



#define    PI_PROT_OVRRD             0x00000008    /*
                                                    * Clear CPU
                                                    * Protection bit in 
                                                    * CPU_PROTECT
                                                    */



#define    PI_IO_PROTECT             0x00000010    /*
                                                    * Interrupt Pending
                                                    * Protection for IO
                                                    * access
                                                    */



#define    PI_REGION_PRESENT         0x00000018    /* Region present         */



#define    PI_CPU_NUM                0x00000020    /* CPU Number ID          */



#define    PI_CALIAS_SIZE            0x00000028    /* Cached Alias Size      */



#define    PI_MAX_CRB_TIMEOUT        0x00000030    /*
                                                    * Maximum Timeout for
                                                    * CRB
                                                    */



#define    PI_CRB_SFACTOR            0x00000038    /*
                                                    * Scale Factor for
                                                    * CRB Timeout
                                                    */



#define    PI_CPU_PRESENT_A          0x00000040    /*
                                                    * CPU Present for
                                                    * CPU_A
                                                    */



#define    PI_CPU_PRESENT_B          0x00000048    /*
                                                    * CPU Present for
                                                    * CPU_B
                                                    */



#define    PI_CPU_ENABLE_A           0x00000050    /*
                                                    * CPU Enable for
                                                    * CPU_A
                                                    */



#define    PI_CPU_ENABLE_B           0x00000058    /*
                                                    * CPU Enable for
                                                    * CPU_B
                                                    */



#define    PI_REPLY_LEVEL            0x00010060    /*
                                                    * Reply FIFO Priority
                                                    * Control
                                                    */



#define    PI_GFX_CREDIT_MODE        0x00020068    /*
                                                    * Graphics Credit
                                                    * Mode
                                                    */



#define    PI_NMI_A                  0x00000070    /*
                                                    * Non-maskable
                                                    * Interrupt to CPU A
                                                    */



#define    PI_NMI_B                  0x00000078    /*
                                                    * Non-maskable
                                                    * Interrupt to CPU B
                                                    */



#define    PI_INT_PEND_MOD           0x00000090    /*
                                                    * Interrupt Pending
                                                    * Modify
                                                    */



#define    PI_INT_PEND0              0x00000098    /* Interrupt Pending 0    */



#define    PI_INT_PEND1              0x000000A0    /* Interrupt Pending 1    */



#define    PI_INT_MASK0_A            0x000000A8    /*
                                                    * Interrupt Mask 0
                                                    * for CPU A
                                                    */



#define    PI_INT_MASK1_A            0x000000B0    /*
                                                    * Interrupt Mask 1
                                                    * for CPU A
                                                    */



#define    PI_INT_MASK0_B            0x000000B8    /*
                                                    * Interrupt Mask 0
                                                    * for CPU B
                                                    */



#define    PI_INT_MASK1_B            0x000000C0    /*
                                                    * Interrupt Mask 1
                                                    * for CPU B
                                                    */



#define    PI_CC_PEND_SET_A          0x000000C8    /*
                                                    * CC Interrupt
                                                    * Pending for CPU A
                                                    */



#define    PI_CC_PEND_SET_B          0x000000D0    /*
                                                    * CC Interrupt
                                                    * Pending for CPU B
                                                    */



#define    PI_CC_PEND_CLR_A          0x000000D8    /*
                                                    * CPU to CPU
                                                    * Interrupt Pending
                                                    * Clear for CPU A
                                                    */



#define    PI_CC_PEND_CLR_B          0x000000E0    /*
                                                    * CPU to CPU
                                                    * Interrupt Pending
                                                    * Clear for CPU B
                                                    */



#define    PI_CC_MASK                0x000000E8    /*
                                                    * Mask of both
                                                    * CC_PENDs
                                                    */



#define    PI_INT_PEND1_REMAP        0x000000F0    /*
                                                    * Remap Interrupt
                                                    * Pending
                                                    */



#define    PI_RT_COUNTER             0x00030100    /* Real Time Counter      */



#define    PI_RT_COMPARE_A           0x00000108    /* Real Time Compare A    */



#define    PI_RT_COMPARE_B           0x00000110    /* Real Time Compare B    */



#define    PI_PROFILE_COMPARE        0x00000118    /* Profiling Compare      */



#define    PI_RT_INT_PEND_A          0x00000120    /*
                                                    * RT interrupt
                                                    * pending
                                                    */



#define    PI_RT_INT_PEND_B          0x00000128    /*
                                                    * RT interrupt
                                                    * pending
                                                    */



#define    PI_PROF_INT_PEND_A        0x00000130    /*
                                                    * Profiling interrupt
                                                    * pending
                                                    */



#define    PI_PROF_INT_PEND_B        0x00000138    /*
                                                    * Profiling interrupt
                                                    * pending
                                                    */



#define    PI_RT_INT_EN_A            0x00000140    /* RT Interrupt Enable    */



#define    PI_RT_INT_EN_B            0x00000148    /* RT Interrupt Enable    */



#define    PI_PROF_INT_EN_A          0x00000150    /*
                                                    * Profiling Interrupt
                                                    * Enable
                                                    */



#define    PI_PROF_INT_EN_B          0x00000158    /*
                                                    * Profiling Interrupt
                                                    * Enable
                                                    */



#define    PI_DEBUG_SEL              0x00000160    /* PI Debug Select        */



#define    PI_INT_PEND_MOD_ALIAS     0x00000180    /*
                                                    * Interrupt Pending
                                                    * Modify
                                                    */



#define    PI_PERF_CNTL_A            0x00040200    /*
                                                    * Performance Counter
                                                    * Control A
                                                    */



#define    PI_PERF_CNTR0_A           0x00040208    /*
                                                    * Performance Counter
                                                    * 0 A
                                                    */



#define    PI_PERF_CNTR1_A           0x00040210    /*
                                                    * Performance Counter
                                                    * 1 A
                                                    */



#define    PI_PERF_CNTL_B            0x00050200    /*
                                                    * Performance Counter
                                                    * Control B
                                                    */



#define    PI_PERF_CNTR0_B           0x00050208    /*
                                                    * Performance Counter
                                                    * 0 B
                                                    */



#define    PI_PERF_CNTR1_B           0x00050210    /*
                                                    * Performance Counter
                                                    * 1 B
                                                    */



#define    PI_GFX_PAGE_A             0x00000300    /* Graphics Page          */



#define    PI_GFX_CREDIT_CNTR_A      0x00000308    /*
                                                    * Graphics Credit
                                                    * Counter
                                                    */



#define    PI_GFX_BIAS_A             0x00000310    /* TRex+ BIAS             */



#define    PI_GFX_INT_CNTR_A         0x00000318    /*
                                                    * Graphics Interrupt
                                                    * Counter
                                                    */



#define    PI_GFX_INT_CMP_A          0x00000320    /*
                                                    * Graphics Interrupt
                                                    * Compare
                                                    */



#define    PI_GFX_PAGE_B             0x00000328    /* Graphics Page          */



#define    PI_GFX_CREDIT_CNTR_B      0x00000330    /*
                                                    * Graphics Credit
                                                    * Counter
                                                    */



#define    PI_GFX_BIAS_B             0x00000338    /* TRex+ BIAS             */



#define    PI_GFX_INT_CNTR_B         0x00000340    /*
                                                    * Graphics Interrupt
                                                    * Counter
                                                    */



#define    PI_GFX_INT_CMP_B          0x00000348    /*
                                                    * Graphics Interrupt
                                                    * Compare
                                                    */



#define    PI_ERR_INT_PEND_WR        0x000003F8    /*