📄 hubmd.h
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} md_led0_fld_s;} md_led0_u_t;#endif/************************************************************************ * * * Each of these addresses allows the value on one 8-bit bank of * * LEDs to be read. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_led1_u { bdrkreg_t md_led1_regval; struct { bdrkreg_t l_data : 8; bdrkreg_t l_reserved : 56; } md_led1_fld_s;} md_led1_u_t;#elsetypedef union md_led1_u { bdrkreg_t md_led1_regval; struct { bdrkreg_t l_reserved : 56; bdrkreg_t l_data : 8; } md_led1_fld_s;} md_led1_u_t;#endif/************************************************************************ * * * Each of these addresses allows the value on one 8-bit bank of * * LEDs to be read. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_led2_u { bdrkreg_t md_led2_regval; struct { bdrkreg_t l_data : 8; bdrkreg_t l_reserved : 56; } md_led2_fld_s;} md_led2_u_t;#elsetypedef union md_led2_u { bdrkreg_t md_led2_regval; struct { bdrkreg_t l_reserved : 56; bdrkreg_t l_data : 8; } md_led2_fld_s;} md_led2_u_t;#endif/************************************************************************ * * * Each of these addresses allows the value on one 8-bit bank of * * LEDs to be read. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_led3_u { bdrkreg_t md_led3_regval; struct { bdrkreg_t l_data : 8; bdrkreg_t l_reserved : 56; } md_led3_fld_s;} md_led3_u_t;#elsetypedef union md_led3_u { bdrkreg_t md_led3_regval; struct { bdrkreg_t l_reserved : 56; bdrkreg_t l_data : 8; } md_led3_fld_s;} md_led3_u_t;#endif/************************************************************************ * * * Core control for the BIST function. Start and stop BIST at any * * time. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_bist_ctl_u { bdrkreg_t md_bist_ctl_regval; struct { bdrkreg_t bc_bist_start : 1; bdrkreg_t bc_bist_stop : 1; bdrkreg_t bc_bist_reset : 1; bdrkreg_t bc_reserved_1 : 1; bdrkreg_t bc_bank_num : 1; bdrkreg_t bc_dimm_num : 2; bdrkreg_t bc_reserved : 57; } md_bist_ctl_fld_s;} md_bist_ctl_u_t;#elsetypedef union md_bist_ctl_u { bdrkreg_t md_bist_ctl_regval; struct { bdrkreg_t bc_reserved : 57; bdrkreg_t bc_dimm_num : 2; bdrkreg_t bc_bank_num : 1; bdrkreg_t bc_reserved_1 : 1; bdrkreg_t bc_bist_reset : 1; bdrkreg_t bc_bist_stop : 1; bdrkreg_t bc_bist_start : 1; } md_bist_ctl_fld_s;} md_bist_ctl_u_t;#endif/************************************************************************ * * * Contain the initial BIST data nibble and the 4-bit data control * * field.. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_bist_data_u { bdrkreg_t md_bist_data_regval; struct { bdrkreg_t bd_bist_data : 4; bdrkreg_t bd_bist_nibble : 1; bdrkreg_t bd_bist_byte : 1; bdrkreg_t bd_bist_cycle : 1; bdrkreg_t bd_bist_write : 1; bdrkreg_t bd_reserved : 56; } md_bist_data_fld_s;} md_bist_data_u_t;#elsetypedef union md_bist_data_u { bdrkreg_t md_bist_data_regval; struct { bdrkreg_t bd_reserved : 56; bdrkreg_t bd_bist_write : 1; bdrkreg_t bd_bist_cycle : 1; bdrkreg_t bd_bist_byte : 1; bdrkreg_t bd_bist_nibble : 1; bdrkreg_t bd_bist_data : 4; } md_bist_data_fld_s;} md_bist_data_u_t;#endif/************************************************************************ * * * Captures the BIST error address and indicates whether it is an MB * * error or DB error. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_bist_ab_err_addr_u { bdrkreg_t md_bist_ab_err_addr_regval; struct { bdrkreg_t baea_be_db_cas_addr : 15; bdrkreg_t baea_reserved_3 : 1; bdrkreg_t baea_be_mb_cas_addr : 15; bdrkreg_t baea_reserved_2 : 1; bdrkreg_t baea_be_ras_addr : 15; bdrkreg_t baea_reserved_1 : 1; bdrkreg_t baea_bist_mb_error : 1; bdrkreg_t baea_bist_db_error : 1; bdrkreg_t baea_reserved : 14; } md_bist_ab_err_addr_fld_s;} md_bist_ab_err_addr_u_t;#elsetypedef union md_bist_ab_err_addr_u { bdrkreg_t md_bist_ab_err_addr_regval; struct { bdrkreg_t baea_reserved : 14; bdrkreg_t baea_bist_db_error : 1; bdrkreg_t baea_bist_mb_error : 1; bdrkreg_t baea_reserved_1 : 1; bdrkreg_t baea_be_ras_addr : 15; bdrkreg_t baea_reserved_2 : 1; bdrkreg_t baea_be_mb_cas_addr : 15; bdrkreg_t baea_reserved_3 : 1; bdrkreg_t baea_be_db_cas_addr : 15; } md_bist_ab_err_addr_fld_s;} md_bist_ab_err_addr_u_t;#endif/************************************************************************ * * * Contains information on BIST progress and memory bank currently * * under BIST. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_bist_status_u { bdrkreg_t md_bist_status_regval; struct { bdrkreg_t bs_bist_passed : 1; bdrkreg_t bs_bist_done : 1; bdrkreg_t bs_reserved : 62; } md_bist_status_fld_s;} md_bist_status_u_t;#elsetypedef union md_bist_status_u { bdrkreg_t md_bist_status_regval; struct { bdrkreg_t bs_reserved : 62; bdrkreg_t bs_bist_done : 1; bdrkreg_t bs_bist_passed : 1; } md_bist_status_fld_s;} md_bist_status_u_t;#endif/************************************************************************ * * * Contains 3 bits that allow the selection of IB debug information * * at the debug port (see design specification for available debug * * information). * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_ib_debug_u { bdrkreg_t md_ib_debug_regval; struct { bdrkreg_t id_ib_debug_sel : 2; bdrkreg_t id_reserved : 62; } md_ib_debug_fld_s;} md_ib_debug_u_t;#elsetypedef union md_ib_debug_u { bdrkreg_t md_ib_debug_regval; struct { bdrkreg_t id_reserved : 62; bdrkreg_t id_ib_debug_sel : 2; } md_ib_debug_fld_s;} md_ib_debug_u_t;#endif/************************************************************************ * * * Contains the directory specific mode bits. The contents of this * * register are preserved through soft-resets. * * * ************************************************************************/#ifdef LITTLE_ENDIANtypedef union md_dir_config_u { bdrkreg_t md_dir_config_regval; struct { bdrkreg_t dc_dir_flavor : 1; bdrkreg_t dc_ignore_dir_ecc : 1; bdrkreg_t dc_reserved : 62; } md_dir_config_fld_s;} md_dir_config_u_t;#elsetypedef union md_dir_config_u { bdrkreg_t md_dir_config_regval; struct { bdrkreg_t dc_reserved : 62; bdrkreg_t dc_ignore_dir_ecc : 1; bdrkreg_t dc_dir_flavor : 1; } md_dir_config_fld_s;} md_dir_config_u_t;#endif/************************************************************************ * * * Description: Contains information on uncorrectable and * * correctable directory ECC errors, along with protection ECC * * errors. The priority of ECC errors latched is: uncorrectable * * directory, protection error, correctable directory. Thus the valid * * bits signal: * * 1xxx: uncorrectable directory ECC error (UCE) * * 01xx: access protection double bit error (AE) * * 001x: correctable directory ECC error (CE) * * 0001: access protection correctable error (ACE) * * If the UCE valid bit is set, the address field contains a pointer * * to the Hspec address of the offending directory entry, the * * syndrome field contains the bad syndrome, and the UCE overrun bit * * indicates whether multiple double-bit errors were received. * * If the UCE valid bit is clear but the AE valid bit is set, the * * address field contains a pointer to the Hspec address of the * * offending protection entry, the Bad Protection field contains the * * 4-bit bad protection value, the PROT_INDEX field shows which of *
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