hubmd.h

上传linux-jx2410的源代码

	struct  {
		bdrkreg_t	mec_reserved_1            :	 3;
		bdrkreg_t       mec_address               :     38;
		bdrkreg_t       mec_reserved              :      7;
		bdrkreg_t       mec_xb_error              :      4;
		bdrkreg_t       mec_bad_partial_data      :      2;
		bdrkreg_t       mec_missing_dv            :      2;
		bdrkreg_t       mec_short_pack            :      2;
		bdrkreg_t       mec_long_pack             :      2;
		bdrkreg_t       mec_ill_msg               :      2;
		bdrkreg_t       mec_ill_revision          :      2;
	} md_misc1_error_clr_fld_s;
} md_misc1_error_clr_u_t;

#else

typedef union md_misc1_error_clr_u {
	bdrkreg_t	md_misc1_error_clr_regval;
	struct	{
		bdrkreg_t	mec_ill_revision	  :	 2;
		bdrkreg_t	mec_ill_msg		  :	 2;
		bdrkreg_t	mec_long_pack		  :	 2;
		bdrkreg_t	mec_short_pack		  :	 2;
		bdrkreg_t	mec_missing_dv		  :	 2;
		bdrkreg_t	mec_bad_partial_data	  :	 2;
		bdrkreg_t	mec_xb_error		  :	 4;
		bdrkreg_t	mec_reserved		  :	 7;
		bdrkreg_t	mec_address		  :	38;
		bdrkreg_t	mec_reserved_1		  :	 3;
	} md_misc1_error_clr_fld_s;
} md_misc1_error_clr_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  The MD no longer allows for arbitrarily sizing the     *
 * reply queues, so all of the fields in this register are read-only    *
 * and contain the reset default value of 12 for the MOQHs (for         *
 * headers) and 24 for the MOQDs (for data).                            *
 * Reading from this register returns the values currently held in      *
 * the MD's credit counters. Writing to the register resets the         *
 * counters to the default reset values specified in the table below.   *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_outgoing_rp_queue_size_u {
	bdrkreg_t	md_outgoing_rp_queue_size_regval;
	struct  {
		bdrkreg_t	orqs_reserved_6           :	 8;
		bdrkreg_t       orqs_moqh_p0_rp_size      :      4;
		bdrkreg_t       orqs_reserved_5           :      4;
		bdrkreg_t       orqs_moqh_p1_rp_size      :      4;
		bdrkreg_t       orqs_reserved_4           :      4;
		bdrkreg_t       orqs_moqh_np_rp_size      :      4;
		bdrkreg_t       orqs_reserved_3           :      4;
		bdrkreg_t       orqs_moqd_pi0_rp_size     :      5;
		bdrkreg_t       orqs_reserved_2           :      3;
		bdrkreg_t       orqs_moqd_pi1_rp_size     :      5;
		bdrkreg_t       orqs_reserved_1           :      3;
		bdrkreg_t       orqs_moqd_np_rp_size      :      5;
		bdrkreg_t       orqs_reserved             :     11;
	} md_outgoing_rp_queue_size_fld_s;
} md_outgoing_rp_queue_size_u_t;

#else

typedef union md_outgoing_rp_queue_size_u {
	bdrkreg_t	md_outgoing_rp_queue_size_regval;
	struct	{
		bdrkreg_t	orqs_reserved		  :	11;
		bdrkreg_t	orqs_moqd_np_rp_size	  :	 5;
		bdrkreg_t	orqs_reserved_1		  :	 3;
		bdrkreg_t	orqs_moqd_pi1_rp_size	  :	 5;
		bdrkreg_t	orqs_reserved_2		  :	 3;
		bdrkreg_t	orqs_moqd_pi0_rp_size	  :	 5;
		bdrkreg_t	orqs_reserved_3		  :	 4;
		bdrkreg_t	orqs_moqh_np_rp_size	  :	 4;
		bdrkreg_t	orqs_reserved_4		  :	 4;
		bdrkreg_t	orqs_moqh_p1_rp_size	  :	 4;
		bdrkreg_t	orqs_reserved_5		  :	 4;
		bdrkreg_t	orqs_moqh_p0_rp_size	  :	 4;
		bdrkreg_t	orqs_reserved_6		  :	 8;
	} md_outgoing_rp_queue_size_fld_s;
} md_outgoing_rp_queue_size_u_t;

#endif






#ifdef LITTLE_ENDIAN

typedef union md_perf_sel0_u {
	bdrkreg_t	md_perf_sel0_regval;
	struct  {
		bdrkreg_t	ps_cnt_mode               :	 2;
		bdrkreg_t       ps_reserved_2             :      2;
		bdrkreg_t       ps_activity               :      4;
		bdrkreg_t       ps_source                 :      7;
		bdrkreg_t       ps_reserved_1             :      1;
		bdrkreg_t       ps_channel                :      4;
		bdrkreg_t       ps_command                :     40;
		bdrkreg_t       ps_reserved               :      3;
		bdrkreg_t       ps_interrupt              :      1;
	} md_perf_sel0_fld_s;
} md_perf_sel0_u_t;

#else

typedef union md_perf_sel0_u {
	bdrkreg_t	md_perf_sel0_regval;
	struct	{
		bdrkreg_t	ps_interrupt		  :	 1;
		bdrkreg_t	ps_reserved		  :	 3;
		bdrkreg_t	ps_command		  :	40;
		bdrkreg_t	ps_channel		  :	 4;
		bdrkreg_t	ps_reserved_1		  :	 1;
		bdrkreg_t	ps_source		  :	 7;
		bdrkreg_t	ps_activity		  :	 4;
		bdrkreg_t	ps_reserved_2		  :	 2;
		bdrkreg_t	ps_cnt_mode		  :	 2;
	} md_perf_sel0_fld_s;
} md_perf_sel0_u_t;

#endif




#ifdef LITTLE_ENDIAN

typedef union md_perf_sel1_u {
	bdrkreg_t	md_perf_sel1_regval;
	struct  {
		bdrkreg_t	ps_cnt_mode               :	 2;
		bdrkreg_t       ps_reserved_2             :      2;
		bdrkreg_t       ps_activity               :      4;
		bdrkreg_t       ps_source                 :      7;
		bdrkreg_t       ps_reserved_1             :      1;
		bdrkreg_t       ps_channel                :      4;
		bdrkreg_t       ps_command                :     40;
		bdrkreg_t       ps_reserved               :      3;
		bdrkreg_t       ps_interrupt              :      1;
	} md_perf_sel1_fld_s;
} md_perf_sel1_u_t;

#else

typedef union md_perf_sel1_u {
	bdrkreg_t	md_perf_sel1_regval;
	struct	{
		bdrkreg_t	ps_interrupt		  :	 1;
		bdrkreg_t	ps_reserved		  :	 3;
		bdrkreg_t	ps_command		  :	40;
		bdrkreg_t	ps_channel		  :	 4;
		bdrkreg_t	ps_reserved_1		  :	 1;
		bdrkreg_t	ps_source		  :	 7;
		bdrkreg_t	ps_activity		  :	 4;
		bdrkreg_t	ps_reserved_2		  :	 2;
		bdrkreg_t	ps_cnt_mode		  :	 2;
	} md_perf_sel1_fld_s;
} md_perf_sel1_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Performance counter.                                                *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_perf_cnt0_u {
	bdrkreg_t	md_perf_cnt0_regval;
	struct  {
		bdrkreg_t	pc_perf_cnt               :	41;
		bdrkreg_t	pc_reserved		  :	23;
	} md_perf_cnt0_fld_s;
} md_perf_cnt0_u_t;

#else

typedef union md_perf_cnt0_u {
	bdrkreg_t	md_perf_cnt0_regval;
	struct	{
		bdrkreg_t	pc_reserved		  :	23;
		bdrkreg_t	pc_perf_cnt		  :	41;
	} md_perf_cnt0_fld_s;
} md_perf_cnt0_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Performance counter.                                                *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_perf_cnt1_u {
	bdrkreg_t	md_perf_cnt1_regval;
	struct  {
		bdrkreg_t	pc_perf_cnt               :	41;
		bdrkreg_t	pc_reserved		  :	23;
	} md_perf_cnt1_fld_s;
} md_perf_cnt1_u_t;

#else

typedef union md_perf_cnt1_u {
	bdrkreg_t	md_perf_cnt1_regval;
	struct	{
		bdrkreg_t	pc_reserved		  :	23;
		bdrkreg_t	pc_perf_cnt		  :	41;
	} md_perf_cnt1_fld_s;
} md_perf_cnt1_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  This register contains the control for                 *
 * memory/directory refresh. Once the MEMORY_CONFIG register contains   *
 * the correct DIMM information, the hardware takes care of             *
 * refreshing all the banks in the system. Therefore, the value in      *
 * the counter threshold is corresponds exactly to the refresh value    *
 * required by the SDRAM parts (expressed in Bedrock clock cycles).     *
 * The refresh will execute whenever there is a free cycle and there    *
 * are still banks that have not been refreshed in the current          *
 * window. If the window expires with banks still waiting to be         *
 * refreshed, all other transactions are halted until the banks are     *
 * refreshed.                                                           *
 * The upper order bit contains an enable, which may be needed for      *
 * correct initialization of the DIMMs (according to the specs, the     *
 * first operation to the DIMMs should be a mode register write, not    *
 * a refresh, so this bit is cleared on reset) and is also useful for   *
 * diagnostic purposes.                                                 *
 * For the SDRAM parts used by Bedrock, 4096 refreshes need to be       *
 * issued during every 64 ms window, resulting in a refresh threshold   *
 * of 3125 Bedrock cycles.                                              *
 * The ENABLE and CNT_THRESH fields of this register are preserved      *
 * through soft-resets.                                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_refresh_control_u {
	bdrkreg_t	md_refresh_control_regval;
	struct  {
		bdrkreg_t	rc_cnt_thresh             :	12;
		bdrkreg_t       rc_counter                :     12;
		bdrkreg_t       rc_reserved               :     39;
		bdrkreg_t       rc_enable                 :      1;
	} md_refresh_control_fld_s;
} md_refresh_control_u_t;

#else

typedef union md_refresh_control_u {
	bdrkreg_t	md_refresh_control_regval;
	struct	{
		bdrkreg_t	rc_enable		  :	 1;
		bdrkreg_t	rc_reserved		  :	39;
		bdrkreg_t	rc_counter		  :	12;
		bdrkreg_t	rc_cnt_thresh		  :	12;
	} md_refresh_control_fld_s;
} md_refresh_control_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  This register controls the read and write timing for Flash PROM,    *
 * UART and Synergy junk bus devices.                                   *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_junk_bus_timing_u {
	bdrkreg_t	md_junk_bus_timing_regval;
	struct  {
		bdrkreg_t	jbt_fprom_setup_hold      :	 8;
		bdrkreg_t       jbt_fprom_enable          :      8;
		bdrkreg_t       jbt_uart_setup_hold       :      8;
		bdrkreg_t       jbt_uart_enable           :      8;
		bdrkreg_t       jbt_synergy_setup_hold    :      8;
		bdrkreg_t       jbt_synergy_enable        :      8;
		bdrkreg_t       jbt_reserved              :     16;
	} md_junk_bus_timing_fld_s;
} md_junk_bus_timing_u_t;

#else

typedef union md_junk_bus_timing_u {
	bdrkreg_t	md_junk_bus_timing_regval;
	struct	{
		bdrkreg_t	jbt_reserved		  :	16;
		bdrkreg_t	jbt_synergy_enable	  :	 8;
		bdrkreg_t	jbt_synergy_setup_hold	  :	 8;
		bdrkreg_t	jbt_uart_enable		  :	 8;
		bdrkreg_t	jbt_uart_setup_hold	  :	 8;
		bdrkreg_t	jbt_fprom_enable	  :	 8;
		bdrkreg_t	jbt_fprom_setup_hold	  :	 8;
	} md_junk_bus_timing_fld_s;
} md_junk_bus_timing_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Each of these addresses allows the value on one 8-bit bank of       *
 * LEDs to be read.                                                     *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_led0_u {
	bdrkreg_t	md_led0_regval;
	struct  {
		bdrkreg_t	l_data                    :	 8;
		bdrkreg_t       l_reserved                :     56;
	} md_led0_fld_s;
} md_led0_u_t;

#else

typedef union md_led0_u {
	bdrkreg_t	md_led0_regval;
	struct	{
		bdrkreg_t	l_reserved		  :	56;
		bdrkreg_t	l_data			  :	 8;