hubmd.h

上传linux-jx2410的源代码

 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_memory_config_u {
	bdrkreg_t	md_memory_config_regval;
	struct  {
		bdrkreg_t	mc_dimm0_bank_enable      :	 2;
		bdrkreg_t       mc_reserved_7             :      1;
		bdrkreg_t       mc_dimm0_dram_width       :      1;
		bdrkreg_t       mc_dimm0_bank_size        :      4;
		bdrkreg_t       mc_dimm1_bank_enable      :      2;
		bdrkreg_t       mc_reserved_6             :      1;
		bdrkreg_t       mc_dimm1_dram_width       :      1;
		bdrkreg_t       mc_dimm1_bank_size        :      4;
                bdrkreg_t       mc_dimm2_bank_enable      :      2;
                bdrkreg_t       mc_reserved_5             :      1;
                bdrkreg_t       mc_dimm2_dram_width       :      1;
                bdrkreg_t       mc_dimm2_bank_size        :      4;
                bdrkreg_t       mc_dimm3_bank_enable      :      2;
                bdrkreg_t       mc_reserved_4             :      1;
                bdrkreg_t       mc_dimm3_dram_width       :      1;
                bdrkreg_t       mc_dimm3_bank_size        :      4;
                bdrkreg_t       mc_dimm0_sel              :      2;
                bdrkreg_t       mc_reserved_3             :     10;
                bdrkreg_t       mc_cc_enable              :      1;
                bdrkreg_t       mc_io_prot_en             :      1;
                bdrkreg_t       mc_io_prot_ignore         :      1;
                bdrkreg_t       mc_cpu_prot_ignore        :      1;
                bdrkreg_t       mc_db_neg_edge            :      1;
                bdrkreg_t       mc_phase_delay            :      1;
                bdrkreg_t       mc_delay_mux_sel          :      2;
                bdrkreg_t       mc_sample_time            :      2;
                bdrkreg_t       mc_reserved_2             :      2;
                bdrkreg_t       mc_mb_neg_edge            :      3;
                bdrkreg_t       mc_reserved_1             :      1;
                bdrkreg_t       mc_rcd_config             :      1;
                bdrkreg_t       mc_rp_config              :      1;
                bdrkreg_t       mc_reserved               :      2;
	} md_memory_config_fld_s;
} md_memory_config_u_t;

#else

typedef union md_memory_config_u {
	bdrkreg_t	md_memory_config_regval;
	struct	{
		bdrkreg_t	mc_reserved		  :	 2;
		bdrkreg_t	mc_rp_config		  :	 1;
		bdrkreg_t	mc_rcd_config		  :	 1;
		bdrkreg_t	mc_reserved_1		  :	 1;
		bdrkreg_t	mc_mb_neg_edge		  :	 3;
		bdrkreg_t	mc_reserved_2		  :	 2;
		bdrkreg_t	mc_sample_time		  :	 2;
		bdrkreg_t	mc_delay_mux_sel	  :	 2;
		bdrkreg_t	mc_phase_delay		  :	 1;
		bdrkreg_t	mc_db_neg_edge		  :	 1;
		bdrkreg_t	mc_cpu_prot_ignore	  :	 1;
		bdrkreg_t	mc_io_prot_ignore	  :	 1;
		bdrkreg_t	mc_io_prot_en		  :	 1;
		bdrkreg_t	mc_cc_enable		  :	 1;
		bdrkreg_t	mc_reserved_3		  :	10;
		bdrkreg_t	mc_dimm0_sel		  :	 2;
		bdrkreg_t	mc_dimm3_bank_size	  :	 4;
		bdrkreg_t	mc_dimm3_dram_width	  :	 1;
		bdrkreg_t	mc_reserved_4		  :	 1;
		bdrkreg_t	mc_dimm3_bank_enable	  :	 2;
		bdrkreg_t	mc_dimm2_bank_size	  :	 4;
		bdrkreg_t	mc_dimm2_dram_width	  :	 1;
		bdrkreg_t	mc_reserved_5		  :	 1;
		bdrkreg_t	mc_dimm2_bank_enable	  :	 2;
		bdrkreg_t	mc_dimm1_bank_size	  :	 4;
		bdrkreg_t	mc_dimm1_dram_width	  :	 1;
		bdrkreg_t	mc_reserved_6		  :	 1;
		bdrkreg_t	mc_dimm1_bank_enable	  :	 2;
		bdrkreg_t	mc_dimm0_bank_size	  :	 4;
		bdrkreg_t	mc_dimm0_dram_width	  :	 1;
		bdrkreg_t	mc_reserved_7		  :	 1;
		bdrkreg_t	mc_dimm0_bank_enable	  :	 2;
	} md_memory_config_fld_s;
} md_memory_config_u_t;

#endif






#ifdef LITTLE_ENDIAN

typedef union md_arbitration_control_u {
	bdrkreg_t	md_arbitration_control_regval;
	struct  {
		bdrkreg_t	ac_reply_guar             :	 4;
		bdrkreg_t       ac_write_guar             :      4;
		bdrkreg_t       ac_reserved               :     56;
	} md_arbitration_control_fld_s;
} md_arbitration_control_u_t;

#else

typedef union md_arbitration_control_u {
	bdrkreg_t	md_arbitration_control_regval;
	struct	{
		bdrkreg_t	ac_reserved		  :	56;
		bdrkreg_t	ac_write_guar		  :	 4;
		bdrkreg_t	ac_reply_guar		  :	 4;
	} md_arbitration_control_fld_s;
} md_arbitration_control_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Contains page migration control fields.                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_mig_config_u {
	bdrkreg_t	md_mig_config_regval;
	struct  {
		bdrkreg_t	mc_mig_interval           :	10;
		bdrkreg_t       mc_reserved_2             :      6;
		bdrkreg_t       mc_mig_node_mask          :      8;
		bdrkreg_t       mc_reserved_1             :      8;
		bdrkreg_t       mc_mig_enable             :      1;
		bdrkreg_t       mc_reserved               :     31;
	} md_mig_config_fld_s;
} md_mig_config_u_t;

#else

typedef union md_mig_config_u {
	bdrkreg_t	md_mig_config_regval;
	struct	{
		bdrkreg_t	mc_reserved		  :	31;
		bdrkreg_t	mc_mig_enable		  :	 1;
		bdrkreg_t	mc_reserved_1		  :	 8;
		bdrkreg_t	mc_mig_node_mask	  :	 8;
		bdrkreg_t	mc_reserved_2		  :	 6;
		bdrkreg_t	mc_mig_interval		  :	10;
	} md_mig_config_fld_s;
} md_mig_config_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Each register contains the valid bit and address of the entry in    *
 * the fetch-and-op for cache 0 (or 1).                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_fandop_cac_stat0_u {
	bdrkreg_t	md_fandop_cac_stat0_regval;
	struct  {
		bdrkreg_t	fcs_reserved_1            :	 6;
		bdrkreg_t       fcs_addr                  :     27;
		bdrkreg_t       fcs_reserved              :     30;
		bdrkreg_t       fcs_valid                 :      1;
	} md_fandop_cac_stat0_fld_s;
} md_fandop_cac_stat0_u_t;

#else

typedef union md_fandop_cac_stat0_u {
	bdrkreg_t	md_fandop_cac_stat0_regval;
	struct	{
		bdrkreg_t	fcs_valid		  :	 1;
		bdrkreg_t	fcs_reserved		  :	30;
		bdrkreg_t	fcs_addr		  :	27;
		bdrkreg_t	fcs_reserved_1		  :	 6;
	} md_fandop_cac_stat0_fld_s;
} md_fandop_cac_stat0_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Each register contains the valid bit and address of the entry in    *
 * the fetch-and-op for cache 0 (or 1).                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_fandop_cac_stat1_u {
	bdrkreg_t	md_fandop_cac_stat1_regval;
	struct  {
		bdrkreg_t	fcs_reserved_1            :	 6;
		bdrkreg_t       fcs_addr                  :     27;
		bdrkreg_t       fcs_reserved              :     30;
		bdrkreg_t       fcs_valid                 :      1;
	} md_fandop_cac_stat1_fld_s;
} md_fandop_cac_stat1_u_t;

#else

typedef union md_fandop_cac_stat1_u {
	bdrkreg_t	md_fandop_cac_stat1_regval;
	struct	{
		bdrkreg_t	fcs_valid		  :	 1;
		bdrkreg_t	fcs_reserved		  :	30;
		bdrkreg_t	fcs_addr		  :	27;
		bdrkreg_t	fcs_reserved_1		  :	 6;
	} md_fandop_cac_stat1_fld_s;
} md_fandop_cac_stat1_u_t;

#endif




/************************************************************************
 *                                                                      *
 * Description:  Contains a number of fields to capture various         *
 * random memory/directory errors. For each 2-bit field, the LSB        *
 * indicates that additional information has been captured for the      *
 * error and the MSB indicates overrun, thus:                           *
 *  x1: bits 51...0 of this register contain additional information     *
 * for the message that caused this error                               *
 *  1x: overrun occurred                                                *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_misc0_error_u {
	bdrkreg_t	md_misc0_error_regval;
	struct	{
		bdrkreg_t	me_command		  :	 7;
                bdrkreg_t       me_reserved_4             :      1;
                bdrkreg_t       me_source                 :     11;
                bdrkreg_t       me_reserved_3             :      1;
                bdrkreg_t       me_suppl                  :     11;
                bdrkreg_t       me_reserved_2             :      1;
                bdrkreg_t       me_virtual_channel        :      2;
                bdrkreg_t       me_reserved_1             :      2;
                bdrkreg_t       me_tail                   :      1;
                bdrkreg_t       me_reserved               :     11;
                bdrkreg_t       me_xb_error               :      4;
                bdrkreg_t       me_bad_partial_data       :      2;
                bdrkreg_t       me_missing_dv             :      2;
                bdrkreg_t       me_short_pack             :      2;
                bdrkreg_t       me_long_pack              :      2;
                bdrkreg_t       me_ill_msg                :      2;
                bdrkreg_t       me_ill_revision           :      2;
	} md_misc0_error_fld_s;
} md_misc0_error_u_t;

#else

typedef union md_misc0_error_u {
	bdrkreg_t	md_misc0_error_regval;
	struct  {
		bdrkreg_t	me_ill_revision           :	 2;
		bdrkreg_t	me_ill_msg                :	 2;
		bdrkreg_t	me_long_pack              :	 2;
		bdrkreg_t	me_short_pack             :	 2;
		bdrkreg_t	me_missing_dv             :	 2;
		bdrkreg_t	me_bad_partial_data       :	 2;
		bdrkreg_t	me_xb_error               :	 4;
		bdrkreg_t	me_reserved               :	11;
		bdrkreg_t	me_tail                   :	 1;
		bdrkreg_t	me_reserved_1             :	 2;
		bdrkreg_t	me_virtual_channel        :	 2;
		bdrkreg_t	me_reserved_2             :	 1;
		bdrkreg_t	me_suppl                  :	11;
		bdrkreg_t	me_reserved_3             :	 1;
		bdrkreg_t	me_source                 :	11;
		bdrkreg_t	me_reserved_4             :	 1;
		bdrkreg_t	me_command                :	 7;
	} md_misc0_error_fld_s;
} md_misc0_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Address for error captured in MISC0_ERROR. Error valid bits are     *
 * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be    *
 * read sequentially without missing any errors).                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_misc1_error_u {
	bdrkreg_t	md_misc1_error_regval;
	struct  {
		bdrkreg_t	me_reserved_1             :	 3;
		bdrkreg_t       me_address                :     38;
		bdrkreg_t       me_reserved               :      7;
		bdrkreg_t       me_xb_error               :      4;
		bdrkreg_t       me_bad_partial_data       :      2;
		bdrkreg_t       me_missing_dv             :      2;
		bdrkreg_t       me_short_pack             :      2;
		bdrkreg_t       me_long_pack              :      2;
		bdrkreg_t       me_ill_msg                :      2;
		bdrkreg_t       me_ill_revision           :      2;
	} md_misc1_error_fld_s;
} md_misc1_error_u_t;

#else

typedef union md_misc1_error_u {
	bdrkreg_t	md_misc1_error_regval;
	struct	{
		bdrkreg_t	me_ill_revision		  :	 2;
		bdrkreg_t	me_ill_msg		  :	 2;
		bdrkreg_t	me_long_pack		  :	 2;
		bdrkreg_t	me_short_pack		  :	 2;
		bdrkreg_t	me_missing_dv		  :	 2;
		bdrkreg_t	me_bad_partial_data	  :	 2;
		bdrkreg_t	me_xb_error		  :	 4;
		bdrkreg_t	me_reserved		  :	 7;
		bdrkreg_t	me_address		  :	38;
		bdrkreg_t	me_reserved_1		  :	 3;
	} md_misc1_error_fld_s;
} md_misc1_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Address for error captured in MISC0_ERROR. Error valid bits are     *
 * repeated in both MISC0_ERROR and MISC1_ERROR (allowing them to be    *
 * read sequentially without missing any errors).                       *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union md_misc1_error_clr_u {
	bdrkreg_t	md_misc1_error_clr_regval;