hubmd.h

上传linux-jx2410的源代码

/* $Id: hubmd.h,v 1.1.1.1 2004/02/04 12:57:43 laputa Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2000 by Colin Ngam
 */
#ifndef _ASM_SN_SN1_HUBMD_H
#define _ASM_SN_SN1_HUBMD_H


/************************************************************************
 *                                                                      *
 *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
 *                                                                      *
 * This file is created by an automated script. Any (minimal) changes   *
 * made manually to this  file should be made with care.                *
 *                                                                      *
 *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
 *                                                                      *
 ************************************************************************/


#define    MD_CURRENT_CELL           0x00780000    /*
                                                    * BDDIR, LREG, LBOOT,
                                                    * RREG, RBOOT
                                                    * protection and mask
                                                    * for using Local
                                                    * Access protection.
                                                    */



#define    MD_MEMORY_CONFIG          0x00780008    /*
                                                    * Memory/Directory
                                                    * DIMM control
                                                    */



#define    MD_ARBITRATION_CONTROL    0x00780010    /*
                                                    * Arbitration
                                                    * Parameters
                                                    */



#define    MD_MIG_CONFIG             0x00780018    /*
                                                    * Page Migration
                                                    * control
                                                    */



#define    MD_FANDOP_CAC_STAT0       0x00780020    /*
                                                    * Fetch-and-op cache
                                                    * 0 status
                                                    */



#define    MD_FANDOP_CAC_STAT1       0x00780028    /*
                                                    * Fetch-and-op cache
                                                    * 1 status
                                                    */



#define    MD_MISC0_ERROR            0x00780040    /*
                                                    * Miscellaneous MD
                                                    * error
                                                    */



#define    MD_MISC1_ERROR            0x00780048    /*
                                                    * Miscellaneous MD
                                                    * error
                                                    */



#define    MD_MISC1_ERROR_CLR        0x00780058    /*
                                                    * Miscellaneous MD
                                                    * error clear
                                                    */



#define    MD_OUTGOING_RP_QUEUE_SIZE 0x00780060    /*
                                                    * MD outgoing reply
                                                    * queues sizing
                                                    */



#define    MD_PERF_SEL0              0x00790000    /*
                                                    * Selects events
                                                    * monitored by
                                                    * MD_PERF_CNT0
                                                    */



#define    MD_PERF_SEL1              0x00790008    /*
                                                    * Selects events
                                                    * monitored by
                                                    * MD_PERF_CNT1
                                                    */



#define    MD_PERF_CNT0              0x00790010    /*
                                                    * Performance counter
                                                    * 0
                                                    */



#define    MD_PERF_CNT1              0x00790018    /*
                                                    * Performance counter
                                                    * 1
                                                    */



#define    MD_REFRESH_CONTROL        0x007A0000    /*
                                                    * Memory/Directory
                                                    * refresh control
                                                    */



#define    MD_JUNK_BUS_TIMING        0x007A0008    /* Junk Bus Timing        */



#define    MD_LED0                   0x007A0010    /* Reads of 8-bit LED0    */



#define    MD_LED1                   0x007A0018    /* Reads of 8-bit LED1    */



#define    MD_LED2                   0x007A0020    /* Reads of 8-bit LED2    */



#define    MD_LED3                   0x007A0028    /* Reads of 8-bit LED3    */



#define    MD_BIST_CTL               0x007A0030    /*
                                                    * BIST general
                                                    * control
                                                    */



#define    MD_BIST_DATA              0x007A0038    /*
                                                    * BIST initial data
                                                    * pattern and
                                                    * variation control
                                                    */



#define    MD_BIST_AB_ERR_ADDR       0x007A0040    /* BIST error address     */



#define    MD_BIST_STATUS            0x007A0048    /* BIST status            */



#define    MD_IB_DEBUG               0x007A0060    /* IB debug select        */



#define    MD_DIR_CONFIG             0x007C0000    /*
                                                    * Directory mode
                                                    * control
                                                    */



#define    MD_DIR_ERROR              0x007C0010    /*
                                                    * Directory DIMM
                                                    * error
                                                    */



#define    MD_DIR_ERROR_CLR          0x007C0018    /*
                                                    * Directory DIMM
                                                    * error clear
                                                    */



#define    MD_PROTOCOL_ERROR         0x007C0020    /*
                                                    * Directory protocol
                                                    * error
                                                    */



#define    MD_PROTOCOL_ERR_CLR       0x007C0028    /*
                                                    * Directory protocol
                                                    * error clear
                                                    */



#define    MD_MIG_CANDIDATE          0x007C0030    /*
                                                    * Page migration
                                                    * candidate
                                                    */



#define    MD_MIG_CANDIDATE_CLR      0x007C0038    /*
                                                    * Page migration
                                                    * candidate clear
                                                    */



#define    MD_MIG_DIFF_THRESH        0x007C0040    /*
                                                    * Page migration
                                                    * count difference
                                                    * threshold
                                                    */



#define    MD_MIG_VALUE_THRESH       0x007C0048    /*
                                                    * Page migration
                                                    * count absolute
                                                    * threshold
                                                    */



#define    MD_OUTGOING_RQ_QUEUE_SIZE 0x007C0050    /*
                                                    * MD outgoing request
                                                    * queues sizing
                                                    */



#define    MD_BIST_DB_ERR_DATA       0x007C0058    /*
                                                    * BIST directory
                                                    * error data
                                                    */



#define    MD_DB_DEBUG               0x007C0060    /* DB debug select        */



#define    MD_MB_ECC_CONFIG          0x007E0000    /*
                                                    * Data ECC
                                                    * Configuration
                                                    */



#define    MD_MEM_ERROR              0x007E0010    /* Memory DIMM error      */



#define    MD_MEM_ERROR_CLR          0x007E0018    /*
                                                    * Memory DIMM error
                                                    * clear
                                                    */



#define    MD_BIST_MB_ERR_DATA_0     0x007E0020    /*
                                                    * BIST memory error
                                                    * data
                                                    */



#define    MD_BIST_MB_ERR_DATA_1     0x007E0028    /*
                                                    * BIST memory error
                                                    * data
                                                    */



#define    MD_BIST_MB_ERR_DATA_2     0x007E0030    /*
                                                    * BIST memory error
                                                    * data
                                                    */



#define    MD_BIST_MB_ERR_DATA_3     0x007E0038    /*
                                                    * BIST memory error
                                                    * data
                                                    */



#define    MD_MB_DEBUG               0x007E0040    /* MB debug select        */





#ifdef _LANGUAGE_C

/************************************************************************
 *                                                                      *
 * Description:  This register shows which regions are in the current   *
 * cell. If a region has its bit set in this register, then it uses     *
 * the Local Access protection in the directory instead of the          *
 * separate per-region protection (which would cause a small            *
 * performance penalty). In addition, writeback and write reply         *
 * commands from outside the current cell will always check the         *
 * directory protection before writing data to memory. Writeback and    *
 * write reply commands from inside the current cell will write         *
 * memory regardless of the protection value.                           *
 * This register is also used as the access-rights bit-vector for       *
 * most of the ASIC-special (HSpec) portion of the address space. It    *
 * covers the BDDIR, LREG, LBOOT, RREG, and RBOOT spaces. It does not   *
 * cover the UALIAS and BDECC spaces, as they are covered by the        *
 * protection in the directory. If a bit in the bit-vector is set,      *
 * the region corresponding to that bit has read/write permission on    *
 * these spaces. If the bit is clear, then that region has read-only    *
 * access to these spaces (except for LREG/RREG which have no access    *
 * when the bit is clear).                                              *
 * The granularity of a region is set by the REGION_SIZE register in    *
 * the NI local register space.                                         *
 * NOTE: This means that no processor outside the current cell can      *
 * write into the BDDIR, LREG, LBOOT, RREG, or RBOOT spaces.            *
 *                                                                      *
 ************************************************************************/




typedef union md_current_cell_u {
	bdrkreg_t	md_current_cell_regval;
	struct  {
		bdrkreg_t	cc_hspec_prot             :	64;
	} md_current_cell_fld_s;
} md_current_cell_u_t;




/************************************************************************
 *                                                                      *
 * Description:  This register contains three sets of information.      *
 * The first set describes the size and configuration of DIMMs that     *
 * are plugged into a system, the second set controls which set of      *
 * protection checks are performed on each access and the third set     *
 * controls various DDR SDRAM timing parameters.                        *
 * In order to config a DIMM bank, three fields must be initialized:    *
 * BANK_SIZE, DRAM_WIDTH, and BANK_ENABLE. The BANK_SIZE field sets     *
 * the address range that the MD unit will accept for that DIMM bank.   *
 * All addresses larger than the specified size will return errors on   *
 * access. In order to read from a DIMM bank, Bedrock must know         *
 * whether or not the bank contains x4 or x8/x16 DRAM. The operating    *
 * system must query the System Controller for this information and     *
 * then set the DRAM_WIDTH field accordingly. The BANK_ENABLE field     *
 * can be used to individually enable the two physical banks located    *
 * on each DIMM bank.                                                   *
 * The contents of this register are preserved through soft-resets.     *