hubxb.h

上传linux-jx2410的源代码

		bdrkreg_t	ddc_observe_miq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_niq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_iiq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_liq_traffic	  :	 1;
	} xb_debug_data_ctl_fld_s;
} xb_debug_data_ctl_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Controls debug mux setting for XB Input/Output Queues and           *
 * Arbiter. Can select one of the following values. Details on the      *
 * debug output lines can be found in the XB chapter of the Bedrock     *
 * Interface Specification.                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_debug_arb_ctl_u {
	bdrkreg_t	xb_debug_arb_ctl_regval;
	struct  {
		bdrkreg_t	dac_xb_debug_select       :	 3;
		bdrkreg_t       dac_rsrvd                 :     61;
	} xb_debug_arb_ctl_fld_s;
} xb_debug_arb_ctl_u_t;

#else

typedef union xb_debug_arb_ctl_u {
        bdrkreg_t       xb_debug_arb_ctl_regval;
        struct  {
                bdrkreg_t       dac_rsrvd                 :     61;
                bdrkreg_t       dac_xb_debug_select       :      3;
        } xb_debug_arb_ctl_fld_s;
} xb_debug_arb_ctl_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by POQ0.Can be written to test software, will   *
 * cause an interrupt.                                                  *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_poq0_error_clear_u {
	bdrkreg_t	xb_poq0_error_clear_regval;
	struct  {
		bdrkreg_t	pec_invalid_xsel          :	 2;
                bdrkreg_t       pec_rsrvd_3               :      2;
                bdrkreg_t       pec_overflow              :      2;
                bdrkreg_t       pec_rsrvd_2               :      2;
                bdrkreg_t       pec_underflow             :      2;
                bdrkreg_t       pec_rsrvd_1               :      2;
                bdrkreg_t       pec_tail_timeout          :      2;
                bdrkreg_t       pec_unused                :      6;
                bdrkreg_t       pec_rsrvd                 :     44;
	} xb_poq0_error_clear_fld_s;
} xb_poq0_error_clear_u_t;

#else

typedef union xb_poq0_error_clear_u {
	bdrkreg_t	xb_poq0_error_clear_regval;
	struct	{
		bdrkreg_t	pec_rsrvd		  :	44;
		bdrkreg_t	pec_unused		  :	 6;
		bdrkreg_t	pec_tail_timeout	  :	 2;
		bdrkreg_t	pec_rsrvd_1		  :	 2;
		bdrkreg_t	pec_underflow		  :	 2;
		bdrkreg_t	pec_rsrvd_2		  :	 2;
		bdrkreg_t	pec_overflow		  :	 2;
		bdrkreg_t	pec_rsrvd_3		  :	 2;
		bdrkreg_t	pec_invalid_xsel	  :	 2;
	} xb_poq0_error_clear_fld_s;
} xb_poq0_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
 * precludes PIQ underflow.                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_piq0_error_clear_u {
	bdrkreg_t	xb_piq0_error_clear_regval;
	struct  {
		bdrkreg_t	pec_overflow              :	 2;
                bdrkreg_t       pec_rsrvd_1               :      2;
                bdrkreg_t       pec_deadlock_timeout      :      2;
                bdrkreg_t       pec_rsrvd                 :     58;
	} xb_piq0_error_clear_fld_s;
} xb_piq0_error_clear_u_t;

#else

typedef union xb_piq0_error_clear_u {
	bdrkreg_t	xb_piq0_error_clear_regval;
	struct	{
		bdrkreg_t	pec_rsrvd		  :	58;
		bdrkreg_t	pec_deadlock_timeout	  :	 2;
		bdrkreg_t	pec_rsrvd_1		  :	 2;
		bdrkreg_t	pec_overflow		  :	 2;
	} xb_piq0_error_clear_fld_s;
} xb_piq0_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
 * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
 * errors are possible.                                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_mp0_error_clear_u {
	bdrkreg_t	xb_mp0_error_clear_regval;
	struct  {
		bdrkreg_t	mec_rsrvd_3               :	 4;
                bdrkreg_t       mec_overflow              :      2;
                bdrkreg_t       mec_rsrvd_2               :      2;
                bdrkreg_t       mec_underflow             :      2;
                bdrkreg_t       mec_rsrvd_1               :      2;
                bdrkreg_t       mec_tail_timeout          :      2;
                bdrkreg_t       mec_rsrvd                 :     50;
	} xb_mp0_error_clear_fld_s;
} xb_mp0_error_clear_u_t;

#else

typedef union xb_mp0_error_clear_u {
	bdrkreg_t	xb_mp0_error_clear_regval;
	struct	{
		bdrkreg_t	mec_rsrvd		  :	50;
		bdrkreg_t	mec_tail_timeout	  :	 2;
		bdrkreg_t	mec_rsrvd_1		  :	 2;
		bdrkreg_t	mec_underflow		  :	 2;
		bdrkreg_t	mec_rsrvd_2		  :	 2;
		bdrkreg_t	mec_overflow		  :	 2;
		bdrkreg_t	mec_rsrvd_3		  :	 4;
	} xb_mp0_error_clear_fld_s;
} xb_mp0_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by MIQ.                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_xm_miq_error_clear_u {
	bdrkreg_t	xb_xm_miq_error_clear_regval;
	struct  {
		bdrkreg_t	xmec_rsrvd_1              :	 4;
                bdrkreg_t       xmec_deadlock_timeout     :      4;
                bdrkreg_t       xmec_rsrvd                :     56;
	} xb_xm_miq_error_clear_fld_s;
} xb_xm_miq_error_clear_u_t;

#else

typedef union xb_xm_miq_error_clear_u {
	bdrkreg_t	xb_xm_miq_error_clear_regval;
	struct	{
		bdrkreg_t	xmec_rsrvd		  :	56;
		bdrkreg_t	xmec_deadlock_timeout	  :	 4;
		bdrkreg_t	xmec_rsrvd_1		  :	 4;
	} xb_xm_miq_error_clear_fld_s;
} xb_xm_miq_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by NOQ.                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_noq_error_clear_u {
	bdrkreg_t	xb_noq_error_clear_regval;
	struct  {
		bdrkreg_t	nec_rsvd                  :	 4;
                bdrkreg_t       nec_overflow              :      4;
                bdrkreg_t       nec_underflow             :      4;
                bdrkreg_t       nec_tail_timeout          :      4;
                bdrkreg_t       nec_rsrvd                 :     48;
	} xb_noq_error_clear_fld_s;
} xb_noq_error_clear_u_t;

#else

typedef union xb_noq_error_clear_u {
	bdrkreg_t	xb_noq_error_clear_regval;
	struct	{
		bdrkreg_t	nec_rsrvd		  :	48;
		bdrkreg_t	nec_tail_timeout	  :	 4;
		bdrkreg_t	nec_underflow		  :	 4;
		bdrkreg_t	nec_overflow		  :	 4;
		bdrkreg_t	nec_rsvd		  :	 4;
	} xb_noq_error_clear_fld_s;
} xb_noq_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by LOQ.                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_loq_error_clear_u {
	bdrkreg_t	xb_loq_error_clear_regval;
	struct  {
		bdrkreg_t	lec_invalid_xsel          :	 2;
                bdrkreg_t       lec_rsrvd_1               :      6;
                bdrkreg_t       lec_underflow             :      2;
                bdrkreg_t       lec_rsvd                  :      2;
                bdrkreg_t       lec_tail_timeout          :      2;
                bdrkreg_t       lec_rsrvd                 :     50;
	} xb_loq_error_clear_fld_s;
} xb_loq_error_clear_u_t;

#else

typedef union xb_loq_error_clear_u {
	bdrkreg_t	xb_loq_error_clear_regval;
	struct	{
		bdrkreg_t	lec_rsrvd		  :	50;
		bdrkreg_t	lec_tail_timeout	  :	 2;
		bdrkreg_t	lec_rsvd		  :	 2;
		bdrkreg_t	lec_underflow		  :	 2;
		bdrkreg_t	lec_rsrvd_1		  :	 6;
		bdrkreg_t	lec_invalid_xsel	  :	 2;
	} xb_loq_error_clear_fld_s;
} xb_loq_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by LIQ. Note that the LIQ only records errors   *
 * for the request channel. The reply channel can never deadlock or     *
 * overflow because it does not have hardware flow control.             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_liq_error_clear_u {
	bdrkreg_t	xb_liq_error_clear_regval;
	struct  {
		bdrkreg_t	lec_overflow              :	 1;
                bdrkreg_t       lec_rsrvd_1               :      3;
                bdrkreg_t       lec_deadlock_timeout      :      1;
                bdrkreg_t       lec_rsrvd                 :     59;
	} xb_liq_error_clear_fld_s;
} xb_liq_error_clear_u_t;

#else

typedef union xb_liq_error_clear_u {
        bdrkreg_t       xb_liq_error_clear_regval;
        struct  {
                bdrkreg_t       lec_rsrvd                 :     59;
                bdrkreg_t       lec_deadlock_timeout      :      1;
                bdrkreg_t       lec_rsrvd_1               :      3;
                bdrkreg_t       lec_overflow              :      1;
        } xb_liq_error_clear_fld_s;
} xb_liq_error_clear_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  First error is latched whenever the Valid bit is clear and an       *
 * error occurs. Any valid bit on in this register causes an            *
 * interrupt to PI0 and PI1. This interrupt bit will persist until      *
 * the specific error register to capture the error is cleared, then    *
 * the FIRST_ERROR register is cleared (in that oder.) The              *
 * FIRST_ERROR register is not writable, but will be set when any of    *
 * the corresponding error registers are written by software.           *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_first_error_clear_u {
	bdrkreg_t	xb_first_error_clear_regval;
	struct  {
		bdrkreg_t	fec_type                  :	 4;
                bdrkreg_t       fec_channel               :      4;
                bdrkreg_t       fec_source                :      4;
                bdrkreg_t       fec_valid                 :      1;
                bdrkreg_t       fec_rsrvd                 :     51;
	} xb_first_error_clear_fld_s;
} xb_first_error_clear_u_t;

#else

typedef union xb_first_error_clear_u {
	bdrkreg_t	xb_first_error_clear_regval;
	struct	{
		bdrkreg_t	fec_rsrvd		  :	51;
		bdrkreg_t	fec_valid		  :	 1;
		bdrkreg_t	fec_source		  :	 4;
		bdrkreg_t	fec_channel		  :	 4;
		bdrkreg_t	fec_type		  :	 4;
	} xb_first_error_clear_fld_s;
} xb_first_error_clear_u_t;

#endif






#endif /* _LANGUAGE_C */

/************************************************************************
 *                                                                      *
 * The following defines were not formed into structures                *
 *                                                                      *
 * This could be because the document did not contain details of the    *
 * register, or because the automated script did not recognize the      *
 * register details in the documentation. If these register need        *
 * structure definition, please create them manually                    *
 *                                                                      *
 *           XB_POQ1_ERROR            0x700030                          *
 *           XB_PIQ1_ERROR            0x700038                          *
 *           XB_MP1_ERROR             0x700048                          *
 *           XB_MMQ_ERROR             0x700050                          *
 *           XB_NIQ_ERROR             0x700068                          *
 *           XB_IOQ_ERROR             0x700070                          *
 *           XB_IIQ_ERROR             0x700078                          *
 *           XB_POQ1_ERROR_CLEAR      0x700130                          *
 *           XB_PIQ1_ERROR_CLEAR      0x700138                          *
 *           XB_MP1_ERROR_CLEAR       0x700148                          *
 *           XB_MMQ_ERROR_CLEAR       0x700150                          *
 *           XB_NIQ_ERROR_CLEAR       0x700168                          *
 *           XB_IOQ_ERROR_CLEAR       0x700170                          *
 *           XB_IIQ_ERROR_CLEAR       0x700178                          *
 *                                                                      *
 ************************************************************************/


/************************************************************************
 *                                                                      *
 *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
 *                                                                      *
 ************************************************************************/





#endif /* _ASM_SN_SN1_HUBXB_H */