hubxb.h

上传linux-jx2410的源代码

/************************************************************************
 *                                                                      *
 *  Number of clocks the IOQ will wait before beginning XB              *
 * arbitration. This is set so that the slower IOQ data rate can        *
 * catch up up with the XB data rate in the IOQ buffer.                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_ioq_arb_trigger_u {
	bdrkreg_t	xb_ioq_arb_trigger_regval;
	struct  {
		bdrkreg_t	iat_ioq_arb_trigger       :	 4;
	        bdrkreg_t       iat_rsrvd                 :     60;
	} xb_ioq_arb_trigger_fld_s;
} xb_ioq_arb_trigger_u_t;

#else

typedef union xb_ioq_arb_trigger_u {
	bdrkreg_t	xb_ioq_arb_trigger_regval;
	struct	{
		bdrkreg_t	iat_rsrvd		  :	60;
		bdrkreg_t	iat_ioq_arb_trigger	  :	 4;
	} xb_ioq_arb_trigger_fld_s;
} xb_ioq_arb_trigger_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by POQ0.Can be written to test software, will   *
 * cause an interrupt.                                                  *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_poq0_error_u {
	bdrkreg_t	xb_poq0_error_regval;
	struct  {
		bdrkreg_t	pe_invalid_xsel           :	 2;
                bdrkreg_t       pe_rsrvd_3                :      2;
                bdrkreg_t       pe_overflow               :      2;
                bdrkreg_t       pe_rsrvd_2                :      2;
                bdrkreg_t       pe_underflow              :      2;
                bdrkreg_t       pe_rsrvd_1                :      2;
                bdrkreg_t       pe_tail_timeout           :      2;
                bdrkreg_t       pe_unused                 :      6;
                bdrkreg_t       pe_rsrvd                  :     44;
	} xb_poq0_error_fld_s;
} xb_poq0_error_u_t;

#else

typedef union xb_poq0_error_u {
	bdrkreg_t	xb_poq0_error_regval;
	struct	{
		bdrkreg_t	pe_rsrvd		  :	44;
		bdrkreg_t	pe_unused		  :	 6;
		bdrkreg_t	pe_tail_timeout		  :	 2;
		bdrkreg_t	pe_rsrvd_1		  :	 2;
		bdrkreg_t	pe_underflow		  :	 2;
		bdrkreg_t	pe_rsrvd_2		  :	 2;
		bdrkreg_t	pe_overflow		  :	 2;
		bdrkreg_t	pe_rsrvd_3		  :	 2;
		bdrkreg_t	pe_invalid_xsel		  :	 2;
	} xb_poq0_error_fld_s;
} xb_poq0_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
 * precludes PIQ underflow.                                             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_piq0_error_u {
	bdrkreg_t	xb_piq0_error_regval;
	struct  {
		bdrkreg_t	pe_overflow               :	 2;
                bdrkreg_t       pe_rsrvd_1                :      2;
                bdrkreg_t       pe_deadlock_timeout       :      2;
                bdrkreg_t       pe_rsrvd                  :     58;
	} xb_piq0_error_fld_s;
} xb_piq0_error_u_t;

#else

typedef union xb_piq0_error_u {
	bdrkreg_t	xb_piq0_error_regval;
	struct	{
		bdrkreg_t	pe_rsrvd		  :	58;
		bdrkreg_t	pe_deadlock_timeout	  :	 2;
		bdrkreg_t	pe_rsrvd_1		  :	 2;
		bdrkreg_t	pe_overflow		  :	 2;
	} xb_piq0_error_fld_s;
} xb_piq0_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
 * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
 * errors are possible.                                                 *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_mp0_error_u {
	bdrkreg_t	xb_mp0_error_regval;
	struct  {
		bdrkreg_t	me_rsrvd_3                :	 4;
                bdrkreg_t       me_overflow               :      2;
                bdrkreg_t       me_rsrvd_2                :      2;
                bdrkreg_t       me_underflow              :      2;
                bdrkreg_t       me_rsrvd_1                :      2;
                bdrkreg_t       me_tail_timeout           :      2;
                bdrkreg_t       me_rsrvd                  :     50;
	} xb_mp0_error_fld_s;
} xb_mp0_error_u_t;

#else

typedef union xb_mp0_error_u {
	bdrkreg_t	xb_mp0_error_regval;
	struct	{
		bdrkreg_t	me_rsrvd		  :	50;
		bdrkreg_t	me_tail_timeout		  :	 2;
		bdrkreg_t	me_rsrvd_1		  :	 2;
		bdrkreg_t	me_underflow		  :	 2;
		bdrkreg_t	me_rsrvd_2		  :	 2;
		bdrkreg_t	me_overflow		  :	 2;
		bdrkreg_t	me_rsrvd_3		  :	 4;
	} xb_mp0_error_fld_s;
} xb_mp0_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by MIQ.                                         *
 *                                                                      *
 ************************************************************************/



#ifdef LITTLE_ENDIAN

typedef union xb_miq_error_u {
	bdrkreg_t	xb_miq_error_regval;
	struct  {
		bdrkreg_t	me_rsrvd_1                :	 4;
                bdrkreg_t       me_deadlock_timeout       :      4;
                bdrkreg_t       me_rsrvd                  :     56;
	} xb_miq_error_fld_s;
} xb_miq_error_u_t;

#else

typedef union xb_miq_error_u {
	bdrkreg_t	xb_miq_error_regval;
	struct	{
		bdrkreg_t	me_rsrvd		  :	56;
		bdrkreg_t	me_deadlock_timeout	  :	 4;
		bdrkreg_t	me_rsrvd_1		  :	 4;
	} xb_miq_error_fld_s;
} xb_miq_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by NOQ.                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_noq_error_u {
	bdrkreg_t	xb_noq_error_regval;
	struct  {
		bdrkreg_t	ne_rsvd                   :	 4;
                bdrkreg_t       ne_overflow               :      4;
                bdrkreg_t       ne_underflow              :      4;
                bdrkreg_t       ne_tail_timeout           :      4;
                bdrkreg_t       ne_rsrvd                  :     48;
	} xb_noq_error_fld_s;
} xb_noq_error_u_t;

#else

typedef union xb_noq_error_u {
	bdrkreg_t	xb_noq_error_regval;
	struct	{
		bdrkreg_t	ne_rsrvd		  :	48;
		bdrkreg_t	ne_tail_timeout		  :	 4;
		bdrkreg_t	ne_underflow		  :	 4;
		bdrkreg_t	ne_overflow		  :	 4;
		bdrkreg_t	ne_rsvd			  :	 4;
	} xb_noq_error_fld_s;
} xb_noq_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by LOQ.                                         *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_loq_error_u {
	bdrkreg_t	xb_loq_error_regval;
	struct  {
		bdrkreg_t	le_invalid_xsel           :	 2;
                bdrkreg_t       le_rsrvd_1                :      6;
                bdrkreg_t       le_underflow              :      2;
                bdrkreg_t       le_rsvd                   :      2;
                bdrkreg_t       le_tail_timeout           :      2;
                bdrkreg_t       le_rsrvd                  :     50;
	} xb_loq_error_fld_s;
} xb_loq_error_u_t;

#else

typedef union xb_loq_error_u {
	bdrkreg_t	xb_loq_error_regval;
	struct	{
		bdrkreg_t	le_rsrvd		  :	50;
		bdrkreg_t	le_tail_timeout		  :	 2;
		bdrkreg_t	le_rsvd			  :	 2;
		bdrkreg_t	le_underflow		  :	 2;
		bdrkreg_t	le_rsrvd_1		  :	 6;
		bdrkreg_t	le_invalid_xsel		  :	 2;
	} xb_loq_error_fld_s;
} xb_loq_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Records errors seen by LIQ. Note that the LIQ only records errors   *
 * for the request channel. The reply channel can never deadlock or     *
 * overflow because it does not have hardware flow control.             *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_liq_error_u {
	bdrkreg_t	xb_liq_error_regval;
	struct  {
		bdrkreg_t	le_overflow               :	 1;
                bdrkreg_t       le_rsrvd_1                :      3;
                bdrkreg_t       le_deadlock_timeout       :      1;
                bdrkreg_t       le_rsrvd                  :     59;
	} xb_liq_error_fld_s;
} xb_liq_error_u_t;

#else

typedef union xb_liq_error_u {
	bdrkreg_t	xb_liq_error_regval;
	struct	{
		bdrkreg_t	le_rsrvd		  :	59;
		bdrkreg_t	le_deadlock_timeout	  :	 1;
		bdrkreg_t	le_rsrvd_1		  :	 3;
		bdrkreg_t	le_overflow		  :	 1;
	} xb_liq_error_fld_s;
} xb_liq_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  First error is latched whenever the Valid bit is clear and an       *
 * error occurs. Any valid bit on in this register causes an            *
 * interrupt to PI0 and PI1. This interrupt bit will persist until      *
 * the specific error register to capture the error is cleared, then    *
 * the FIRST_ERROR register is cleared (in that oder.) The              *
 * FIRST_ERROR register is not writable, but will be set when any of    *
 * the corresponding error registers are written by software.           *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_first_error_u {
	bdrkreg_t	xb_first_error_regval;
	struct  {
		bdrkreg_t	fe_type                   :	 4;
                bdrkreg_t       fe_channel                :      4;
                bdrkreg_t       fe_source                 :      4;
                bdrkreg_t       fe_valid                  :      1;
                bdrkreg_t       fe_rsrvd                  :     51;
	} xb_first_error_fld_s;
} xb_first_error_u_t;

#else

typedef union xb_first_error_u {
	bdrkreg_t	xb_first_error_regval;
	struct	{
		bdrkreg_t	fe_rsrvd		  :	51;
		bdrkreg_t	fe_valid		  :	 1;
		bdrkreg_t	fe_source		  :	 4;
		bdrkreg_t	fe_channel		  :	 4;
		bdrkreg_t	fe_type			  :	 4;
	} xb_first_error_fld_s;
} xb_first_error_u_t;

#endif




/************************************************************************
 *                                                                      *
 *  Controls DEBUG_DATA mux setting. Allows user to watch the output    *
 * of any OQ or input of any IQ on the DEBUG port. Note that bits       *
 * 13:0 are one-hot. If more than one bit is set in [13:0], the debug   *
 * output is undefined. Details on the debug output lines can be        *
 * found in the XB chapter of the Bedrock Interface Specification.      *
 *                                                                      *
 ************************************************************************/




#ifdef LITTLE_ENDIAN

typedef union xb_debug_data_ctl_u {
	bdrkreg_t	xb_debug_data_ctl_regval;
	struct  {
		bdrkreg_t	ddc_observe_liq_traffic   :	 1;
                bdrkreg_t       ddc_observe_iiq_traffic   :      1;
                bdrkreg_t       ddc_observe_niq_traffic   :      1;
                bdrkreg_t       ddc_observe_miq_traffic   :      1;
                bdrkreg_t       ddc_observe_piq1_traffic  :      1;
                bdrkreg_t       ddc_observe_piq0_traffic  :      1;
                bdrkreg_t       ddc_observe_loq_traffic   :      1;
                bdrkreg_t       ddc_observe_ioq_traffic   :      1;
                bdrkreg_t       ddc_observe_noq_traffic   :      1;
                bdrkreg_t       ddc_observe_mp1_traffic   :      1;
                bdrkreg_t       ddc_observe_mp0_traffic   :      1;
                bdrkreg_t       ddc_observe_mmq_traffic   :      1;
                bdrkreg_t       ddc_observe_poq1_traffic  :      1;
                bdrkreg_t       ddc_observe_poq0_traffic  :      1;
                bdrkreg_t       ddc_observe_source_field  :      1;
                bdrkreg_t       ddc_observe_lodata        :      1;
                bdrkreg_t       ddc_rsrvd                 :     48;
	} xb_debug_data_ctl_fld_s;
} xb_debug_data_ctl_u_t;

#else

typedef union xb_debug_data_ctl_u {
	bdrkreg_t	xb_debug_data_ctl_regval;
	struct	{
		bdrkreg_t	ddc_rsrvd		  :	48;
		bdrkreg_t	ddc_observe_lodata	  :	 1;
		bdrkreg_t	ddc_observe_source_field  :	 1;
		bdrkreg_t	ddc_observe_poq0_traffic  :	 1;
		bdrkreg_t	ddc_observe_poq1_traffic  :	 1;
		bdrkreg_t	ddc_observe_mmq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_mp0_traffic	  :	 1;
		bdrkreg_t	ddc_observe_mp1_traffic	  :	 1;
		bdrkreg_t	ddc_observe_noq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_ioq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_loq_traffic	  :	 1;
		bdrkreg_t	ddc_observe_piq0_traffic  :	 1;
		bdrkreg_t	ddc_observe_piq1_traffic  :	 1;