bridge.h

上传linux-jx2410的源代码

/* $Id: bridge.h,v 1.1.1.1 2004/02/04 12:57:42 laputa Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
 * Copyright (C) 2000 by Colin Ngam
 */
#ifndef _ASM_SN_PCI_BRIDGE_H
#define _ASM_SN_PCI_BRIDGE_H


/*
 * bridge.h - header file for bridge chip and bridge portion of xbridge chip
 */

#include <asm/sn/xtalk/xwidget.h>

/* I/O page size */

#if _PAGESZ == 4096
#define IOPFNSHIFT		12	/* 4K per mapped page */
#else
#define IOPFNSHIFT		14	/* 16K per mapped page */
#endif				/* _PAGESZ */

#define IOPGSIZE		(1 << IOPFNSHIFT)
#define IOPG(x)			((x) >> IOPFNSHIFT)
#define IOPGOFF(x)		((x) & (IOPGSIZE-1))

/* Bridge RAM sizes */

#define BRIDGE_INTERNAL_ATES	128
#define XBRIDGE_INTERNAL_ATES	1024

#define BRIDGE_ATE_RAM_SIZE     (BRIDGE_INTERNAL_ATES<<3)	/* 1kB ATE */
#define XBRIDGE_ATE_RAM_SIZE    (XBRIDGE_INTERNAL_ATES<<3)	/* 8kB ATE */

#define BRIDGE_CONFIG_BASE	0x20000		/* start of bridge's */
						/* map to each device's */
						/* config space */
#define BRIDGE_CONFIG1_BASE	0x28000		/* type 1 device config space */
#define BRIDGE_CONFIG_END	0x30000
#define BRIDGE_CONFIG_SLOT_SIZE 0x1000		/* each map == 4k */

#define BRIDGE_SSRAM_512K	0x00080000	/* 512kB */
#define BRIDGE_SSRAM_128K	0x00020000	/* 128kB */
#define BRIDGE_SSRAM_64K	0x00010000	/* 64kB */
#define BRIDGE_SSRAM_0K		0x00000000	/* 0kB */

/* ========================================================================
 *    Bridge address map
 */

#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)

#ifdef __cplusplus
extern "C" {
#endif

/*
 * All accesses to bridge hardware registers must be done
 * using 32-bit loads and stores.
 */
typedef uint32_t	bridgereg_t;

typedef uint64_t	bridge_ate_t;

/* pointers to bridge ATEs
 * are always "pointer to volatile"
 */
typedef volatile bridge_ate_t  *bridge_ate_p;

/*
 * It is generally preferred that hardware registers on the bridge
 * are located from C code via this structure.
 *
 * Generated from Bridge spec dated 04oct95
 */

#ifdef LITTLE_ENDIAN

typedef volatile struct bridge_s {

    /* Local Registers				       0x000000-0x00FFFF */

    /* standard widget configuration		       0x000000-0x000057 */
    widget_cfg_t	    b_widget;		    /* 0x000000 */

    /* helper fieldnames for accessing bridge widget */

#define b_wid_id			b_widget.w_id
#define b_wid_stat			b_widget.w_status
#define b_wid_err_upper			b_widget.w_err_upper_addr
#define b_wid_err_lower			b_widget.w_err_lower_addr
#define b_wid_control			b_widget.w_control
#define b_wid_req_timeout		b_widget.w_req_timeout
#define b_wid_int_upper			b_widget.w_intdest_upper_addr
#define b_wid_int_lower			b_widget.w_intdest_lower_addr
#define b_wid_err_cmdword		b_widget.w_err_cmd_word
#define b_wid_llp			b_widget.w_llp_cfg
#define b_wid_tflush			b_widget.w_tflush

    /*
     * we access these through synergy unswizzled space, so the address
     * gets twiddled (i.e. references to 0x4 actually go to 0x0 and vv.)
     * That's why we put the register first and filler second.
     */
    /* bridge-specific widget configuration	       0x000058-0x00007F */
    bridgereg_t             b_wid_aux_err;          /* 0x00005C */
    bridgereg_t		    _pad_000058;

    bridgereg_t             b_wid_resp_upper;       /* 0x000064 */
    bridgereg_t             _pad_000060;

    bridgereg_t             b_wid_resp_lower;       /* 0x00006C */
    bridgereg_t             _pad_000068;

    bridgereg_t             b_wid_tst_pin_ctrl;     /* 0x000074 */
    bridgereg_t             _pad_000070;

    bridgereg_t		    _pad_000078[2];

    /* PMU & Map				       0x000080-0x00008F */
    bridgereg_t             b_dir_map;              /* 0x000084 */
    bridgereg_t             _pad_000080;
    bridgereg_t		    _pad_000088[2];

    /* SSRAM					       0x000090-0x00009F */
    bridgereg_t             b_ram_perr_or_map_fault;/* 0x000094 */
    bridgereg_t             _pad_000090;
#define b_ram_perr  b_ram_perr_or_map_fault	/* Bridge */
#define b_map_fault b_ram_perr_or_map_fault	/* Xbridge */
    bridgereg_t		    _pad_000098[2];

    /* Arbitration				       0x0000A0-0x0000AF */
    bridgereg_t             b_arb;                  /* 0x0000A4 */
    bridgereg_t             _pad_0000A0;
    bridgereg_t		    _pad_0000A8[2];

    /* Number In A Can				       0x0000B0-0x0000BF */
    bridgereg_t             b_nic;                  /* 0x0000B4 */
    bridgereg_t             _pad_0000B0;
    bridgereg_t		    _pad_0000B8[2];

    /* PCI/GIO					       0x0000C0-0x0000FF */
    bridgereg_t             b_bus_timeout;          /* 0x0000C4 */
    bridgereg_t             _pad_0000C0;
#define b_pci_bus_timeout b_bus_timeout

    bridgereg_t             b_pci_cfg;              /* 0x0000CC */
    bridgereg_t             _pad_0000C8;

    bridgereg_t             b_pci_err_upper;        /* 0x0000D4 */
    bridgereg_t             _pad_0000D0;

    bridgereg_t             b_pci_err_lower;        /* 0x0000DC */
    bridgereg_t             _pad_0000D8;
    bridgereg_t		    _pad_0000E0[8];
#define b_gio_err_lower b_pci_err_lower
#define b_gio_err_upper b_pci_err_upper

    /* Interrupt				       0x000100-0x0001FF */
    bridgereg_t             b_int_status;           /* 0x000104 */
    bridgereg_t             _pad_000100;

    bridgereg_t             b_int_enable;           /* 0x00010C */
    bridgereg_t             _pad_000108;

    bridgereg_t             b_int_rst_stat;         /* 0x000114 */
    bridgereg_t             _pad_000110;

    bridgereg_t             b_int_mode;             /* 0x00011C */
    bridgereg_t             _pad_000118;

    bridgereg_t             b_int_device;           /* 0x000124 */
    bridgereg_t             _pad_000120;

    bridgereg_t             b_int_host_err;         /* 0x00012C */
    bridgereg_t             _pad_000128;

    struct {
        bridgereg_t             addr;               /* 0x0001{34,,,6C} */
        bridgereg_t             __pad;              /* 0x0001{30,,,68} */
    } b_int_addr[8];				    /* 0x000130 */

    bridgereg_t             b_err_int_view;         /* 0x000174 */
    bridgereg_t             _pad_000170;

    bridgereg_t             b_mult_int;             /* 0x00017c */
    bridgereg_t             _pad_000178;

    struct {
        bridgereg_t             intr;               /* 0x0001{84,,,BC} */
        bridgereg_t             __pad;              /* 0x0001{80,,,B8} */
    } b_force_always[8];			    /* 0x000180 */

    struct {
        bridgereg_t             intr;               /* 0x0001{C4,,,FC} */
        bridgereg_t             __pad;              /* 0x0001{C0,,,F8} */
    } b_force_pin[8];			    	    /* 0x0001C0 */

    /* Device					       0x000200-0x0003FF */
    struct {
        bridgereg_t             reg;                /* 0x0002{04,,,3C} */
        bridgereg_t             __pad;              /* 0x0002{00,,,38} */
    } b_device[8];				    /* 0x000200 */

    struct {
        bridgereg_t             reg;                /* 0x0002{44,,,7C} */
        bridgereg_t             __pad;              /* 0x0002{40,,,78} */
    } b_wr_req_buf[8];				    /* 0x000240 */

    struct {
        bridgereg_t             reg;                /* 0x0002{84,,,8C} */
        bridgereg_t             __pad;              /* 0x0002{80,,,88} */
    } b_rrb_map[2];				    /* 0x000280 */
#define	b_even_resp	b_rrb_map[0].reg	    /* 0x000284 */
#define	b_odd_resp	b_rrb_map[1].reg	    /* 0x00028C */

    bridgereg_t             b_resp_status;          /* 0x000294 */
    bridgereg_t             _pad_000290;

    bridgereg_t             b_resp_clear;           /* 0x00029C */
    bridgereg_t             _pad_000298;

    bridgereg_t		    _pad_0002A0[24];

    /* Xbridge only */
    struct {
	bridgereg_t	        upper;              /* 0x0003{04,,,F4} */
	bridgereg_t             __pad1;		    /* 0x0003{00,,,F0} */
	bridgereg_t             lower;              /* 0x0003{0C,,,FC} */
	bridgereg_t             __pad2;             /* 0x0003{08,,,F8} */
    } b_buf_addr_match[16];

    /* Performance Monitor Registers (even only) */
    struct {
        bridgereg_t             flush_w_touch;      /* 0x000404,,,5C4 */
        bridgereg_t             __pad1;             /* 0x000400,,,5C0 */

        bridgereg_t             flush_wo_touch;     /* 0x00040C,,,5CC */
        bridgereg_t             __pad2;             /* 0x000408,,,5C8 */

        bridgereg_t             inflight;           /* 0x000414,,,5D4 */
        bridgereg_t             __pad3;             /* 0x000410,,,5D0 */

        bridgereg_t             prefetch;           /* 0x00041C,,,5DC */
        bridgereg_t             __pad4;             /* 0x000418,,,5D8 */

        bridgereg_t             total_pci_retry;    /* 0x000424,,,5E4 */
        bridgereg_t             __pad5;             /* 0x000420,,,5E0 */

        bridgereg_t             max_pci_retry;      /* 0x00042C,,,5EC */
        bridgereg_t             __pad6;             /* 0x000428,,,5E8 */

        bridgereg_t             max_latency;        /* 0x000434,,,5F4 */
        bridgereg_t             __pad7;             /* 0x000430,,,5F0 */

        bridgereg_t             clear_all;          /* 0x00043C,,,5FC */
        bridgereg_t             __pad8;             /* 0x000438,,,5F8 */
    } b_buf_count[8];

    char                    _pad_000600[0x010000 - 0x000600];

    /*
     * The Xbridge has 1024 internal ATE's and the Bridge has 128.
     * Make enough room for the Xbridge ATE's and depend on runtime
     * checks to limit access to bridge ATE's.
     */

    /* Internal Address Translation Entry RAM	       0x010000-0x011fff */
    union {
	bridge_ate_t		wr;		/* write-only */
	struct {
	    bridgereg_t             rd;         /* read-only */
            bridgereg_t             _p_pad;
	}			hi;
    }			    b_int_ate_ram[XBRIDGE_INTERNAL_ATES];

#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd

    /* the xbridge read path for internal ates starts at 0x12000.
     * I don't believe we ever try to read the ates.
     */
    /* Internal Address Translation Entry RAM LOW       0x012000-0x013fff */
    struct {
	bridgereg_t             rd; 
        bridgereg_t             _p_pad;
    }			    xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES];

    char		    _pad_014000[0x20000 - 0x014000];

    /* PCI Device Configuration Spaces		       0x020000-0x027FFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x1000 / 1];
	uint16_t		s[0x1000 / 2];
	uint32_t		l[0x1000 / 4];
	uint64_t		d[0x1000 / 8];
	union {
	    uchar_t		c[0x100 / 1];
	    uint16_t		s[0x100 / 2];
	    uint32_t		l[0x100 / 4];
	    uint64_t		d[0x100 / 8];
	}			f[8];
    } b_type0_cfg_dev[8];			    /* 0x020000 */

    /* PCI Type 1 Configuration Space		       0x028000-0x028FFF */
    union {				/* make all access sizes available. */
	uchar_t			c[0x1000 / 1];
	uint16_t		s[0x1000 / 2];
	uint32_t		l[0x1000 / 4];
	uint64_t		d[0x1000 / 8];
    } b_type1_cfg;				    /* 0x028000-0x029000 */

    char		    _pad_029000[0x007000];  /* 0x029000-0x030000 */

    /* PCI Interrupt Acknowledge Cycle		       0x030000 */