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📄 pci_bus_cvlink.c

📁 上传linux-jx2410的源代码
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			}			else				continue;			device_dev->resource[idx].end = 				device_dev->resource[idx].start + size;			/*			 * Adjust the addresses to go to the SWIZZLE ..			 */			device_dev->resource[idx].start = 				device_dev->resource[idx].start & 0xfffff7ffffffffff;			device_dev->resource[idx].end = 				device_dev->resource[idx].end & 0xfffff7ffffffffff;			res = 0;			res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);			if (device_dev->resource[idx].flags & IORESOURCE_IO) {				cmd |= PCI_COMMAND_IO;				ioport = sn1_allocate_ioports(device_dev->resource[idx].start);				/* device_dev->resource[idx].start = ioport; */				/* device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT */			}			else if (device_dev->resource[idx].flags & IORESOURCE_MEM)				cmd |= PCI_COMMAND_MEMORY;		}		/*		 * Now handle the ROM resource ..		 */		size = device_dev->resource[PCI_ROM_RESOURCE].end -			device_dev->resource[PCI_ROM_RESOURCE].start;		device_dev->resource[PCI_ROM_RESOURCE].start =			(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 				size, 0, PCIIO_BYTE_STREAM);		device_dev->resource[PCI_ROM_RESOURCE].end =			device_dev->resource[PCI_ROM_RESOURCE].start + size;                /*                 * go through synergy swizzled space                 */		device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;		device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;		/*		 * Update the Command Word on the Card.		 */		cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */					   /* bit gets dropped .. no harm */		pci_write_config_word(device_dev, PCI_COMMAND, cmd);		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, &lines);#ifdef BRINGUP		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&			device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {				lines = 1;		}#endif 		device_sysdata = (struct sn1_device_sysdata *)device_dev->sysdata;		device_vertex = device_sysdata->vhdl; 		intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);		bit = intr_handle->pi_irq;		cpuid = intr_handle->pi_cpu;		irq = bit_pos_to_irq(bit);		irq = irq + (cpuid << 8);		pciio_intr_connect(intr_handle, NULL, NULL, NULL);		device_dev->irq = irq;	}#endif	/* REAL_HARDWARE */#if 0{        devfs_handle_t  bridge_vhdl = pci_bus_to_vertex(0);        pcibr_soft_t    pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);        bridge_t        *bridge = pcibr_soft->bs_base;        printk("pci_fixup_ioc3: Before devreg fixup\n");        printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);        printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);        printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);        printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);        printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);        printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);        printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);        printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);}#endif}/* * pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job. * *	Linux PCI Bus numbers are assigned from lowest module_id numbers *	(rack/slot etc.) starting from HUB_WIDGET_ID_MAX down to  *	HUB_WIDGET_ID_MIN: *		widgetnum 15 gets lower Bus Number than widgetnum 14 etc. * *	Given 2 modules 001c01 and 001c02 we get the following mappings: *		001c01, widgetnum 15 = Bus number 0 *		001c01, widgetnum 14 = Bus number 1 *		001c02, widgetnum 15 = Bus number 3 *		001c02, widgetnum 14 = Bus number 4 *		etc. * * The rational for starting Bus Number 0 with Widget number 15 is because  * the system boot disks are always connected via Widget 15 Slot 0 of the  * I-brick.  Linux creates /dev/sd* devices(naming) strating from Bus Number 0  * Therefore, /dev/sda1 will be the first disk, on Widget 15 of the lowest  * module id(Master Cnode) of the system. *	 */static int pci_bus_map_create(devfs_handle_t xtalk){	devfs_handle_t master_node_vertex = NULL;	devfs_handle_t xwidget = NULL;	devfs_handle_t pci_bus = NULL;	hubinfo_t hubinfo = NULL;	xwidgetnum_t widgetnum;	char pathname[128];	graph_error_t rv;	/*	 * Loop throught this vertex and get the Xwidgets ..	 */	for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {        {                int pos;                char dname[256];                pos = devfs_generate_path(xtalk, dname, 256);                printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);        }		sprintf(pathname, "%d", widgetnum);		xwidget = NULL;				/*		 * Example - /hw/module/001c16/Pbrick/xtalk/8 is the xwidget		 *	     /hw/module/001c16/Pbrick/xtalk/8/pci/1 is device		 */		rv = hwgraph_traverse(xtalk, pathname, &xwidget);		if ( (rv != GRAPH_SUCCESS) ) {			if (!xwidget)				continue;		}		sprintf(pathname, "%d/"EDGE_LBL_PCI, widgetnum);		pci_bus = NULL;		if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS)			if (!pci_bus)				continue;		/*		 * Assign the correct bus number and also the nasid of this 		 * pci Xwidget.		 * 		 * Should not be any race here ...		 */		num_bridges++;		busnum_to_pcibr_vhdl[num_bridges - 1] = pci_bus;		/*		 * Get the master node and from there get the NASID.		 */		master_node_vertex = device_master_get(xwidget);		if (!master_node_vertex) {			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", xwidget);		}			hubinfo_get(master_node_vertex, &hubinfo);		if (!hubinfo) {			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", master_node_vertex);			return(1);		} else {			busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;		}		/*		 * Pre assign DMA maps needed for 32 Bits Page Map DMA.		 */		busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(			sizeof(struct sn1_dma_maps_s) * 512, GFP_KERNEL);		if (!busnum_to_atedmamaps[num_bridges - 1])			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, xwidget);		memset(busnum_to_atedmamaps[num_bridges - 1], 0x0, 			sizeof(struct sn1_dma_maps_s) * 512);	}        return(0);}/* * pci_bus_to_hcl_cvlink() - This routine is called after SGI IO Infrastructure    *      initialization has completed to set up the mappings between Xbridge *      and logical pci bus numbers.  We also set up the NASID for each of these *      xbridges. * *      Must be called before pci_init() is invoked. */intpci_bus_to_hcl_cvlink(void) {	devfs_handle_t devfs_hdl = NULL;	devfs_handle_t module_comp = NULL;	devfs_handle_t node = NULL;	devfs_handle_t xtalk = NULL;	graph_vertex_place_t placeptr = EDGE_PLACE_WANT_REAL_EDGES;	int rv = 0;	char name[256];	int master_iobrick;	moduleid_t iobrick_id;	int i;	/*	 * Iterate throught each xtalk links in the system ..	 * /hw/module/001c01/node/xtalk/ 8|9|10|11|12|13|14|15 	 *	 * /hw/module/001c01/node/xtalk/15 -> /hw/module/001c01/Ibrick/xtalk/15	 *	 * What if it is not pci?	 */	devfs_hdl = hwgraph_path_to_vertex("/dev/hw/module");	/*	 * To provide consistent(not persistent) device naming, we need to start 	 * bus number allocation from the C-Brick with the lowest module id e.g. 001c01 	 * with an attached I-Brick.  Find the master_iobrick.	 */	master_iobrick = -1;	for (i = 0; i < nummodules; i++) {		moduleid_t iobrick_id; 		iobrick_id = iobrick_module_get(&modules[i]->elsc);		if (iobrick_id > 0) { /* Valid module id */			if (MODULE_GET_BTYPE(iobrick_id) == MODULE_IBRICK) {				master_iobrick = i;				break;			}		}	}	/*	 * The master_iobrick gets bus 0 and 1.	 */	if (master_iobrick >= 0) {		memset(name, 0, 256);		format_module_id(name, modules[master_iobrick]->id, MODULE_FORMAT_BRIEF);		strcat(name, "/node/xtalk");		xtalk = NULL;		rv = hwgraph_edge_get(devfs_hdl, name, &xtalk);		pci_bus_map_create(xtalk);	}			/*	 * Now go do the rest of the modules, starting from the C-Brick with the lowest 	 * module id, remembering to skip the master_iobrick, which was done above.	 */	for (i = 0; i < nummodules; i++) {		if (i == master_iobrick) {			continue; /* Did the master_iobrick already. */		}		memset(name, 0, 256);		format_module_id(name, modules[i]->id, MODULE_FORMAT_BRIEF);		strcat(name, "/node/xtalk");		xtalk = NULL;		rv = hwgraph_edge_get(devfs_hdl, name, &xtalk);		pci_bus_map_create(xtalk);	}	return(0);}/* * sgi_pci_intr_support - */intsgi_pci_intr_support (unsigned int requested_irq, device_desc_t *dev_desc,	devfs_handle_t *bus_vertex, pciio_intr_line_t *lines,	devfs_handle_t *device_vertex){	unsigned int bus;	unsigned int devfn;	struct pci_dev *pci_dev;	unsigned char intr_pin = 0;	struct sn1_widget_sysdata *widget_sysdata;	struct sn1_device_sysdata *device_sysdata;	if (!dev_desc || !bus_vertex || !device_vertex) {		printk("WARNING: sgi_pci_intr_support: Invalid parameter dev_desc 0x%p, bus_vertex 0x%p, device_vertex 0x%p\n", dev_desc, bus_vertex, device_vertex);		return(-1);	}	devfn = (requested_irq >> 8) & 0xff;	bus = (requested_irq >> 16) & 0xffff;	pci_dev = pci_find_slot(bus, devfn);	widget_sysdata = (struct sn1_widget_sysdata *)pci_dev->bus->sysdata;	*bus_vertex = widget_sysdata->vhdl;	device_sysdata = (struct sn1_device_sysdata *)pci_dev->sysdata;	*device_vertex = device_sysdata->vhdl;#if 0	{		int pos;		char dname[256];		pos = devfs_generate_path(*device_vertex, dname, 256);		printk("%s : path= %s pos %d\n", __FUNCTION__, &dname[pos], pos);	}#endif /* BRINGUP */	/*	 * Get the Interrupt PIN.	 */	pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intr_pin);	*lines = (pciio_intr_line_t)intr_pin;#ifdef BRINGUP	/*	 * ioc3 can't decode the PCI_INTERRUPT_PIN field of its config	 * space so we have to set it here	 */	if (pci_dev->vendor == PCI_VENDOR_ID_SGI &&	    pci_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {		*lines = 1;	}#endif /* BRINGUP */	/* Not supported currently */	*dev_desc = NULL;	return(0);}

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