transcript

用verilog编写的bch译码器

# Reading D:/Modeltech_6.2b/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.2b Jul 31 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do {decoder15_test_v.fdo} 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module decoder15
# 
# Top level modules:
# 	decoder15
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module decoder15_test_v
# 
# Top level modules:
# 	decoder15_test_v
# Model Technology ModelSim SE vlog 6.2b Compiler 2006.07 Jul 31 2006
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps decoder15_test_v glbl 
# Loading work.decoder15_test_v(fast)
# Loading work.decoder15(fast)
# Loading work.glbl(fast)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page2.cs
# .main_pane.signals.interior.cs
add wave sim:/decoder15_test_v/uut/r
add wave sim:/decoder15_test_v/uut/clk
add wave sim:/decoder15_test_v/uut/c
add wave sim:/decoder15_test_v/uut/s1
add wave sim:/decoder15_test_v/uut/s2
add wave sim:/decoder15_test_v/uut/s3
add wave sim:/decoder15_test_v/uut/s4
add wave sim:/decoder15_test_v/uut/s5
add wave sim:/decoder15_test_v/uut/s6
add wave sim:/decoder15_test_v/uut/mymem1
add wave sim:/decoder15_test_v/uut/mymem2
add wave sim:/decoder15_test_v/uut/mymem3
add wave sim:/decoder15_test_v/uut/mymem4
add wave sim:/decoder15_test_v/uut/mymem5
add wave sim:/decoder15_test_v/uut/mymeme
add wave sim:/decoder15_test_v/uut/ee
add wave sim:/decoder15_test_v/uut/mymems
add wave sim:/decoder15_test_v/uut/mymems1
add wave sim:/decoder15_test_v/uut/mymems2
add wave sim:/decoder15_test_v/uut/mymems3
add wave sim:/decoder15_test_v/uut/mymemk1
add wave sim:/decoder15_test_v/uut/mymemk2
add wave sim:/decoder15_test_v/uut/mymemk3
add wave sim:/decoder15_test_v/uut/e
add wave sim:/decoder15_test_v/uut/i
add wave sim:/decoder15_test_v/uut/k
add wave sim:/decoder15_test_v/uut/k2
add wave sim:/decoder15_test_v/uut/k3
add wave sim:/decoder15_test_v/uut/delta1_downk1
add wave sim:/decoder15_test_v/uut/delta1_upk2
add wave sim:/decoder15_test_v/uut/delta2_upk3
add wave sim:/decoder15_test_v/uut/c1
add wave sim:/decoder15_test_v/uut/svalue
add wave sim:/decoder15_test_v/uut/delta1_down
add wave sim:/decoder15_test_v/uut/delta1_up
add wave sim:/decoder15_test_v/uut/delta2_down
add wave sim:/decoder15_test_v/uut/delta2_up
add wave sim:/decoder15_test_v/uut/delta1
add wave sim:/decoder15_test_v/uut/delta2
add wave sim:/decoder15_test_v/uut/delta11
add wave sim:/decoder15_test_v/uut/delta22
restart
# Loading work.decoder15_test_v(fast)
# Loading work.decoder15(fast)
# Loading work.glbl(fast)
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