decoder15_test_v.fdo

来自「用verilog编写的bch译码器」· FDO 代码 · 共 16 行

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun May 18 20:57:48 中国标准时间 2008
##
vlib work
vlog  +acc  "decoder15.v"
vlog  +acc  "decoder15_test.v"
vlog  +acc  "D:/Xilinx92i/verilog/src/glbl.v"
vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -lib work decoder15_test_v glbl
view wave
add wave *
add wave /glbl/GSR
do {decoder15_test_v.udo}
view structure
view signals
run 1000ns