work__info

用verilog编写的bch译码器

m255
13
cModel Technology
dD:\luoqiwu\FPGA\oytt
T_opt
Vm4>FHUWKlgW]OJ[CQ?^<L2
04 4 4 work glbl fast 0
04 16 4 work decoder15_test_v fast 0
o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_ver
tExplicit 1
OE;O;6.2b;35
T_opt1
VTY_9fLbSK^[WbbF4Mki`n1
04 16 4 work decoder15_test_v fast 0
o-quiet -auto_acc_if_foreign -work work -L xilinxcorelib_ver -L unisims_ver
tExplicit 1
OE;O;6.2b;35
vdecoder15
ICF1EbY391ZeIgRRIb1<PP1
Vk[:QPAPMkAJ4iiWKa04`M0
dD:\luoqiwu\FPGA\oytt
w1210732146
Fdecoder15.v
L0 21
Vk[:QPAPMkAJ4iiWKa04`M0
OE;L;6.2b;35
r1
31
o+acc
vdecoder15_test_v
IkEm=<BTZDF05jlV9c8A9k3
V;10eNY<14CMTSSzZ6UYB;1
dD:\luoqiwu\FPGA\oytt
w1210733304
FD:/luoqiwu/FPGA/oytt/decoder15_test.v
L0 25
V;10eNY<14CMTSSzZ6UYB;1
OE;L;6.2b;35
r1
31
o-work work
vglbl
I@25W]P_?R2MF58_YTL5O=0
VnN]4Gon>inod6>M^M2[SV1
dD:\luoqiwu\FPGA\oytt
w1179523376
FD:/Xilinx92i/verilog/src/glbl.v
L0 5
VnN]4Gon>inod6>M^M2[SV1
OE;L;6.2b;35
r1
31
o+acc