lpregs.inc

CYRF6936 zigbee模块设计的全部资料

; single flag bits & multi-bit-field masks
ACK_EN:                                         equ 0x80
FRC_END_STATE:                                  equ 0x20
END_STATE_MSK:                                  equ 0x1c
ACK_TO_MSK:                                     equ 0x03

; END_STATE field values
END_STATE_SLEEP:                                equ 0x00
END_STATE_IDLE:                                 equ 0x04
END_STATE_TXSYNTH:                              equ 0x08
END_STATE_RXSYNTH:                              equ 0x0C
END_STATE_RX:                                   equ 0x10

; ACK_TO field values
ACK_TO_4X:                                      equ 0x00
ACK_TO_8X:                                      equ 0x01
ACK_TO_12X:                                     equ 0x02
ACK_TO_15X:                                     equ 0x03


; -------------------------------
; Framing Configuration register
; -------------------------------
FRAMING_CFG_ADR:                                equ 0x10
FRAMING_CFG_RST:                                equ 0xa5

; single flag bits & multi-bit-field masks
SOP_EN:                                         equ 0x80
SOP_LEN:                                        equ 0x40
LEN_EN:                                         equ 0x20
SOP_THRESH_MSK:                                 equ 0x1f


; -------------------------------
; Data Threshold 32 register
; -------------------------------
DATA32_THOLD_ADR:                               equ 0x11
DAT32_THRESH_RST:                               equ 0x04
DAT32_THRESH_MSK:                               equ 0x0f


; -------------------------------
; Data Threshold 64 register
; -------------------------------
DATA64_THOLD_ADR:                               equ 0x12
DAT64_THRESH_RST:                               equ 0x0a
DAT64_THRESH_MSK:                               equ 0x1f


; -------------------------------
; RSSI register
; -------------------------------
RSSI_ADR:                                       equ 0x13
RSSI_RST:                                       equ 0x20

; single flag bits & multi-bit-field masks
SOP_RSSI:                                       equ 0x80
LNA_STATE:                                      equ 0x20
RSSI_LVL_MSK:                                   equ 0x1f


; -------------------------------
; EOP Control register
; -------------------------------
EOP_CTRL_ADR:                                   equ 0x14
EOP_CTRL_RST:                                   equ 0xa4

; single flag bits & multi-bit-field masks
HINT_EN:                                        equ 0x80
HINT_EOP_MSK:                                   equ 0x70
EOP_MSK:                                        equ 0x0f


; -------------------------------
; CRC Seed registers
; -------------------------------
CRC_SEED_LSB_ADR:                               equ 0x15
CRC_SEED_MSB_ADR:                               equ 0x16
CRC_SEED_LSB_RST:                               equ 0x00
CRC_SEED_MSB_RST:                               equ 0x00

; CRC related values
; USB CRC-16
CRC_POLY_MSB:                                   equ 0x80
CRC_POLY_LSB:                                   equ 0x05
CRC_RESI_MSB:                                   equ 0x80
CRC_RESI_LSB:                                   equ 0x0d


; -------------------------------
; TX CRC Calculated registers
; -------------------------------
TX_CRC_LSB_ADR:                                 equ 0x17
TX_CRC_MSB_ADR:                                 equ 0x18


; -------------------------------
; RX CRC Field registers
; -------------------------------
RX_CRC_LSB_ADR:                                 equ 0x19
RX_CRC_MSB_ADR:                                 equ 0x1a
RX_CRC_LSB_RST:                                 equ 0xff
RX_CRC_MSB_RST:                                 equ 0xff


; -------------------------------
; Synth Offset registers
; -------------------------------
TX_OFFSET_LSB_ADR:                              equ 0x1b
TX_OFFSET_MSB_ADR:                              equ 0x1c
TX_OFFSET_LSB_RST:                              equ 0x00
TX_OFFSET_MSB_RST:                              equ 0x00

; single flag bits & multi-bit-field masks
STRIM_MSB_MSK:                                  equ 0x0f
STRIM_LSB_MSK:                                  equ 0xff


; -------------------------------
; Mode Override register
; -------------------------------
MODE_OVERRIDE_ADR:                              equ 0x1d
MODE_OVERRIDE_RST:                              equ 0x00

FRC_AWAKE:                                      equ 0x03
FRC_AWAKE_OFF_1:                                equ 0x01
FRC_AWAKE_OFF_2:                                equ 0x00

; single flag bits & multi-bit-field masks
DIS_AUTO_SEN:                                   equ 0x80
SEN_TXRXB:                                      equ 0x40
FRC_SEN:                                        equ 0x20
FRC_AWAKE_MSK:                                  equ 0x18
MODE_OVRD_FRC_AWAKE:                            equ 0x18
MODE_OVRD_FRC_AWAKE_OFF_1:                      equ 0x08
MODE_OVRD_FRC_AWAKE_OFF_2:                      equ 0x00
RST:                                            equ 0x01
FRC_PA:                                         equ 0x02


; -------------------------------
; RX Override register
; -------------------------------
RX_OVERRIDE_ADR:                                equ 0x1e
RX_OVERRIDE_RST:                                equ 0x00

; single flag bits & multi-bit-field masks
ACK_RX:                                         equ 0x80
EXTEND_RX_TX:                                   equ 0x40
MAN_RXACK:                                      equ 0x20
FRC_RXDR:                                       equ 0x10
DIS_CRC0:                                       equ 0x08
DIS_RXCRC:                                      equ 0x04
ACE:                                            equ 0x02


; -------------------------------
; TX Override register
; -------------------------------
TX_OVERRIDE_ADR:                                equ 0x1f
TX_OVERRIDE_RST:                                equ 0x00

; single flag bits & multi-bit-field masks
ACK_TX_SEN:                                     equ 0x80
FRC_PREAMBLE:                                   equ 0x40
DIS_TX_RETRANS:                                 equ 0x20
MAN_TXACK:                                      equ 0x10
OVRRD_ACK:                                      equ 0x08
DIS_TXCRC:                                      equ 0x04
CO:                                             equ 0x02
TXINV:                                          equ 0x01


;------------------------------------------------------------------------------
;      File Function Detail
;------------------------------------------------------------------------------

; -------------------------------
; TX Buffer - 16 bytes
; -------------------------------
TX_BUFFER_ADR:                                  equ 0x20


; -------------------------------
; RX Buffer - 16 bytes
; -------------------------------
RX_BUFFER_ADR:                                  equ 0x21


; -------------------------------
; Framing Code - 8 bytes
; -------------------------------
SOP_CODE_ADR:                                   equ 0x22

; CODESTORE_REG_SOF_RST        64'h17_ff_9e_21_36_90_c7_82
CODESTORE_BYTE7_SOF_RST:                        equ 0x17
CODESTORE_BYTE6_SOF_RST:                        equ 0xff
CODESTORE_BYTE5_SOF_RST:                        equ 0x9e
CODESTORE_BYTE4_SOF_RST:                        equ 0x21
CODESTORE_BYTE3_SOF_RST:                        equ 0x36
CODESTORE_BYTE2_SOF_RST:                        equ 0x90
CODESTORE_BYTE1_SOF_RST:                        equ 0xc7
CODESTORE_BYTE0_SOF_RST:                        equ 0x82


; -------------------------------
; Data Code - 16 bytes
; -------------------------------
DATA_CODE_ADR:                                  equ 0x23

; CODESTORE_REG_DCODE0_RST            64'h01_2B_F1_DB_01_32_BE_6F
CODESTORE_BYTE7_DCODE0_RST:                     equ 0x01
CODESTORE_BYTE6_DCODE0_RST:                     equ 0x2b
CODESTORE_BYTE5_DCODE0_RST:                     equ 0xf1
CODESTORE_BYTE4_DCODE0_RST:                     equ 0xdb
CODESTORE_BYTE3_DCODE0_RST:                     equ 0x01
CODESTORE_BYTE2_DCODE0_RST:                     equ 0x32
CODESTORE_BYTE1_DCODE0_RST:                     equ 0xbe
CODESTORE_BYTE0_DCODE0_RST:                     equ 0x6f

; CODESTORE_REG_DCODE1_RST            64'h02_F9_93_97_02_FA_5C_E3
CODESTORE_BYTE7_DCODE1_RST:                     equ 0x02
CODESTORE_BYTE6_DCODE1_RST:                     equ 0xf9
CODESTORE_BYTE5_DCODE1_RST:                     equ 0x93
CODESTORE_BYTE4_DCODE1_RST:                     equ 0x97
CODESTORE_BYTE3_DCODE1_RST:                     equ 0x02
CODESTORE_BYTE2_DCODE1_RST:                     equ 0xfa
CODESTORE_BYTE1_DCODE1_RST:                     equ 0x5c
CODESTORE_BYTE0_DCODE1_RST:                     equ 0xe3


; -------------------------------
; Preamble - 3 bytes
; -------------------------------
PREAMBLE_ADR:                                   equ 0x24

PREAMBLE_CODE_MSB_RST:                          equ 0x33
PREAMBLE_CODE_LSB_RST:                          equ 0x33
PREAMBLE_LEN_RST:                               equ 0x02


; -------------------------------
; Laser Fuses - 8 bytes (2 hidden)
; -------------------------------
MFG_ID_ADR:                                     equ 0x25


; -------------------------------
; XTAL Startup Delay
; -------------------------------
XTAL_CFG_ADR:                                   equ 0x26
XTAL_CFG_RST:                                   equ 0x00

; -------------------------------
; Clock Override
; -------------------------------
CLK_OVERRIDE_ADR:                               equ 0x27
CLK_OVERRIDE_RST:                               equ 0x00

RXF:                                            equ 0x02


; -------------------------------
; Clock Enable
; -------------------------------
CLK_EN_ADR:                                     equ 0x28
CLK_EN_RST:                                     equ 0x00

RXF:                                            equ 0x02


; -------------------------------
; Receiver Abort
; -------------------------------
RX_ABORT_ADR:                                   equ 0x29
RX_ABORT_RST:                                   equ 0x00

ABORT_EN:                                       equ 0x20


; -------------------------------
; Auto Calibration Time
; -------------------------------
AUTO_CAL_TIME_ADR:                              equ 0x32
AUTO_CAL_TIME_RST:                              equ 0x0C

AUTO_CAL_TIME_MAX:                              equ 0x3C


; -------------------------------
; Auto Calibration Offset
; -------------------------------
AUTO_CAL_OFFSET_ADR:                            equ 0x35
AUTO_CAL_OFFSET_RST:                            equ 0x00

AUTO_CAL_OFFSET_MINUS_4:                        equ 0x14