pic18fxx2.h

首先pic和铁电24c02通讯

//SPI Status SSPSTAT
static		near bit		SMP  		@ ((unsigned)&SSPSTAT*8)+7; //Sample Bit
static		near bit		CKE  		@ ((unsigned)&SSPSTAT*8)+6; //SPI Clock Edge Select
static volatile near bit		DA  		@ ((unsigned)&SSPSTAT*8)+5; //Data/Address Bit
static volatile near bit		P  		@ ((unsigned)&SSPSTAT*8)+4; //Stop Bit
static volatile near bit		S  		@ ((unsigned)&SSPSTAT*8)+3; //Start Bit
static volatile near bit		RW  		@ ((unsigned)&SSPSTAT*8)+2; //Read/Write Bit Information
static volatile near bit		UA  		@ ((unsigned)&SSPSTAT*8)+1; //Update Address
static volatile near bit		BF  		@ ((unsigned)&SSPSTAT*8)+0; //Buffer Full Status Bit
/* alternate definitions */
static volatile near bit		STOP  		@ ((unsigned)&SSPSTAT*8)+4; //Stop Bit
static volatile near bit		START  		@ ((unsigned)&SSPSTAT*8)+3; //Start Bit

//SPI Control 1 SSPCON1
static volatile near bit		WCOL  		@ ((unsigned)&SSPCON1*8)+7; //Write Collision Detect
static volatile near bit		SSPOV  		@ ((unsigned)&SSPCON1*8)+6; //Recieve Overflow Detect
static		near bit		SSPEN  		@ ((unsigned)&SSPCON1*8)+5; //Synchronous Serial Port Enable
static		near bit		CKP  		@ ((unsigned)&SSPCON1*8)+4; //Clock Polarity Select
static		near bit		SSPM3  		@ ((unsigned)&SSPCON1*8)+3; //Mode Select Bits
static		near bit		SSPM2  		@ ((unsigned)&SSPCON1*8)+2; //
static		near bit		SSPM1  		@ ((unsigned)&SSPCON1*8)+1; //
static		near bit		SSPM0  		@ ((unsigned)&SSPCON1*8)+0; //

//SPI Control 2 SSPCON2
static		near bit		GCEN  		@ ((unsigned)&SSPCON2*8)+7; //General Call Enable
static volatile near bit		ACKSTAT		@ ((unsigned)&SSPCON2*8)+6; //Acknowledge Status
static volatile near bit		ACKDT		@ ((unsigned)&SSPCON2*8)+5; //Acknowledge Detect
static volatile near bit		ACKEN		@ ((unsigned)&SSPCON2*8)+4; //Acknowledge Sequence Enable
static		near bit		RCEN  		@ ((unsigned)&SSPCON2*8)+3; //Recieve Enable
static volatile near bit		PEN  		@ ((unsigned)&SSPCON2*8)+2; //STOP Condition Enable
static volatile near bit		RSEN		@ ((unsigned)&SSPCON2*8)+1; //Repeated START Condition Enable
static volatile near bit		SEN		@ ((unsigned)&SSPCON2*8)+0; //START Condition Enable/Stretch Enable

//AD Control 0 ADCON0
static		near bit		ADCS1  		@ ((unsigned)&ADCON0*8)+7; //AD Conversion Clock Select Bits
static		near bit		ADCS0		@ ((unsigned)&ADCON0*8)+6; //
static		near bit		CHS2		@ ((unsigned)&ADCON0*8)+5; //Analog Channel Select Bits
static		near bit		CHS1		@ ((unsigned)&ADCON0*8)+4; //
static		near bit		CHS0		@ ((unsigned)&ADCON0*8)+3; //
static volatile near bit		GODONE		@ ((unsigned)&ADCON0*8)+2; //AD Conversion Status
static		near bit		ADON		@ ((unsigned)&ADCON0*8)+0; //AD On/Off

//AD Control 1 ADCON1 
static		near bit		ADFM		@ ((unsigned)&ADCON1*8)+7; //AD Result Format Select
static		near bit		ADCS2		@ ((unsigned)&ADCON1*8)+6; //AD Conv. Clock Select
static		near bit		PCFG3		@ ((unsigned)&ADCON1*8)+3; //AD Port Config. Control bits
static		near bit		PCFG2		@ ((unsigned)&ADCON1*8)+2; //
static		near bit		PCFG1		@ ((unsigned)&ADCON1*8)+1; //
static		near bit		PCFG0		@ ((unsigned)&ADCON1*8)+0; //

//CCP1CON
static volatile near bit		DC1B1		@ ((unsigned)&CCP1CON*8)+5; //Duty Cycle Bits
static volatile near bit		DC1B0		@ ((unsigned)&CCP1CON*8)+4; //
static		near bit		CCP1M3		@ ((unsigned)&CCP1CON*8)+3; //CCP1 Mode Select
static		near bit		CCP1M2		@ ((unsigned)&CCP1CON*8)+2; //
static		near bit		CCP1M1		@ ((unsigned)&CCP1CON*8)+1; //
static		near bit		CCP1M0		@ ((unsigned)&CCP1CON*8)+0; //

//CCP2CON
static volatile near bit		DC2B1		@ ((unsigned)&CCP2CON*8)+5; //Duty Cycle Bits
static volatile near bit	 	DC2B0		@ ((unsigned)&CCP2CON*8)+4; //
static		near bit		CCP2M3		@ ((unsigned)&CCP2CON*8)+3; //CCP2 Mode Select
static		near bit		CCP2M2		@ ((unsigned)&CCP2CON*8)+2; //
static		near bit		CCP2M1		@ ((unsigned)&CCP2CON*8)+1; //
static		near bit		CCP2M0		@ ((unsigned)&CCP2CON*8)+0; //

//Timer 3 Control T3CON
static		near bit		T3RD16		@ ((unsigned)&T3CON*8)+7; //16 Bit Read Write Mode
static		near bit		T3CCP2		@ ((unsigned)&T3CON*8)+6; //TM3/TM1 CCP Clock Select Bits
static		near bit		T3CKPS1		@ ((unsigned)&T3CON*8)+5; //TM3 Clock Input Prescale
static		near bit		T3CKPS0		@ ((unsigned)&T3CON*8)+4; //
static		near bit		T3CCP1		@ ((unsigned)&T3CON*8)+3; //TM3/TM1 CCP Clock Select Bits
static		near bit		T3SYNC		@ ((unsigned)&T3CON*8)+2; //TM3 Ext. Clock Synchronize Select
static		near bit		TMR3CS		@ ((unsigned)&T3CON*8)+1; //TM3 Clock Source Select
static		near bit		TMR3ON		@ ((unsigned)&T3CON*8)+0; //TM3 Enable/Stop

//Transmission Status TXSTA
static		near bit		CSRC		@ ((unsigned)&TXSTA*8)+7; //Clock Source Select
static		near bit		TX9		@ ((unsigned)&TXSTA*8)+6; //9/8 Bit Select
static		near bit		TXEN		@ ((unsigned)&TXSTA*8)+5; //Transmit Enable
static		near bit		SYNC		@ ((unsigned)&TXSTA*8)+4; //USART Select Mode
static		near bit		BRGH		@ ((unsigned)&TXSTA*8)+2; //High Baud rate Select
static volatile near bit		TRMT		@ ((unsigned)&TXSTA*8)+1; //Transmit Shift Register Status Bit
static		near bit		TX9D		@ ((unsigned)&TXSTA*8)+0; //9th Bit of TX data

//Reception Status RCSTA
static		near bit		SPEN		@ ((unsigned)&RCSTA*8)+7; //Serial Port Enable
static		near bit		RX9		@ ((unsigned)&RCSTA*8)+6; //9/8 Bit Select
static		near bit		SREN		@ ((unsigned)&RCSTA*8)+5; //Single Recieve Enable Bit
static		near bit		CREN		@ ((unsigned)&RCSTA*8)+4; //Continous Recieve Enable Bit
static		near bit		ADDEN		@ ((unsigned)&RCSTA*8)+3; //Address detect Enable Bit
static volatile near bit		FERR		@ ((unsigned)&RCSTA*8)+2; //Framing Error
static volatile near bit		OERR		@ ((unsigned)&RCSTA*8)+1; //Overrun Error
static volatile near bit		RX9D		@ ((unsigned)&RCSTA*8)+0; //9th Bit of RX data

//EECON1
static 		near bit		EEPGD		@ ((unsigned)&EECON1*8)+7; //FLASH/EEPROM Select
static 		near bit		CFGS		@ ((unsigned)&EECON1*8)+6; //Config./Calibration Select
// alternate definition
static 		near bit		EEFS		@ ((unsigned)&EECON1*8)+6; //Config./Calibration Select
static volatile near bit		FREE 		@ ((unsigned)&EECON1*8)+4; //FLASH Row Erase Enable
static volatile near bit 		WRERR		@ ((unsigned)&EECON1*8)+3; //EEPROM Error Flag
static volatile near bit		WREN 		@ ((unsigned)&EECON1*8)+2; //EEPROM Write enable
static volatile near bit 		WR		@ ((unsigned)&EECON1*8)+1; //Write Control bit
static volatile near bit 		RD		@ ((unsigned)&EECON1*8)+0; //Read Control bit

//Interrupt Priority 2 IPR2
static 		near bit 		EEIP		@ ((unsigned)&IPR2*8)+4; //EEPROM/FLASH Write Interrupt
static 		near bit 		BCLIP		@ ((unsigned)&IPR2*8)+3; //Bus Collision Interrupt
static 		near bit 		LVDIP		@ ((unsigned)&IPR2*8)+2; //Low Voltage Detect
static 		near bit 		TMR3IP		@ ((unsigned)&IPR2*8)+1; //TMR3 Overflow Interrupt
static 		near bit 		CCP2IP		@ ((unsigned)&IPR2*8)+0; //CCP2 Interrupt

//Periphal Interrupt Request Register 2 PIR2
static volatile near bit 		EEIF		@ ((unsigned)&PIR2*8)+4; //EEPROM/FLASH Write Interrupt
static volatile near bit 		BCLIF		@ ((unsigned)&PIR2*8)+3; //Bus Collision Interrupt
static volatile near bit		LVDIF		@ ((unsigned)&PIR2*8)+2; //Low Voltage Detect
static volatile near bit 		TMR3IF		@ ((unsigned)&PIR2*8)+1; //TMR3 Overflow Interrupt
static volatile near bit 		CCP2IF		@ ((unsigned)&PIR2*8)+0; //CCP2 Interrupt

//Peripheral Interrupt Enable 2 PIE2
static 		near bit 		EEIE		@ ((unsigned)&PIE2*8)+4; //EEPROM/FLASH Write Interrupt
static 		near bit 		BCLIE		@ ((unsigned)&PIE2*8)+3; //Bus Collision Interrupt
static 		near bit		LVDIE		@ ((unsigned)&PIE2*8)+2; //Low Voltage Detect
static 		near bit 		TMR3IE		@ ((unsigned)&PIE2*8)+1; //TMR3 Overflow Interrupt
static 		near bit 		CCP2IE		@ ((unsigned)&PIE2*8)+0; //CCP2 Interrupt

//Interrupt Priority 1 IPR1
static 		near bit 		PSPIP		@ ((unsigned)&IPR1*8)+7; //Parallel Slave Port Read/Write Interrupt
static 		near bit 		ADIP		@ ((unsigned)&IPR1*8)+6; //AD Converter Interrupt
static 		near bit 		RCIP		@ ((unsigned)&IPR1*8)+5; //USART Recieve Interrupt
static 		near bit 		TXIP		@ ((unsigned)&IPR1*8)+4; //USART Transmit Interrupt
static 		near bit 		SSPIP		@ ((unsigned)&IPR1*8)+3; //Master Synchronous Serial Port Interrupt
static 		near bit 		CCP1IP		@ ((unsigned)&IPR1*8)+2; //CCP1 Interrupt
static 		near bit 		TMR2IP		@ ((unsigned)&IPR1*8)+1; //TMR2 Overflow Interrupt
static 		near bit 		TMR1IP		@ ((unsigned)&IPR1*8)+0; //TMR1 Overflow Interrupt

//Peripheral Interrupt Request 1 PIR1
static volatile	near bit 		PSPIF		@ ((unsigned)&PIR1*8)+7; //Parallel Slave Port Read/Write Interrupt
static volatile	near bit 		ADIF		@ ((unsigned)&PIR1*8)+6; //AD Converter Interrupt
static volatile	near bit 		RCIF		@ ((unsigned)&PIR1*8)+5; //USART Recieve Interrupt
static volatile	near bit 		TXIF		@ ((unsigned)&PIR1*8)+4; //USART Transmit Interrupt
static volatile	near bit 		SSPIF		@ ((unsigned)&PIR1*8)+3; //Master Synchronous Serial Port Interrupt
static volatile	near bit 		CCP1IF		@ ((unsigned)&PIR1*8)+2; //CCP1 Interrupt
static volatile	near bit 		TMR2IF		@ ((unsigned)&PIR1*8)+1; //TMR2 Overflow Interrupt
static volatile	near bit 		TMR1IF		@ ((unsigned)&PIR1*8)+0; //TMR1 Overflow Interrupt

//Peripheral Interupt Enable 1 PIE1
static 		near bit 		PSPIE		@ ((unsigned)&PIE1*8)+7; //Parallel Slave Port Read/Write Interrupt
static 		near bit 		ADIE		@ ((unsigned)&PIE1*8)+6; //AD Converter Interrupt
static 		near bit 		RCIE		@ ((unsigned)&PIE1*8)+5; //USART Recieve Interrupt
static 		near bit 		TXIE		@ ((unsigned)&PIE1*8)+4; //USART Transmit Interrupt
static 		near bit 		SSPIE		@ ((unsigned)&PIE1*8)+3; //Master Synchronous Serial Port Interrupt
static 		near bit 		CCP1IE		@ ((unsigned)&PIE1*8)+2; //CCP1 Interrupt
static 		near bit 		TMR2IE		@ ((unsigned)&PIE1*8)+1; //TMR2 Overflow Interrupt
static 		near bit 		TMR1IE		@ ((unsigned)&PIE1*8)+0; //TMR1 Overflow Interrupt

#if defined(_18F442) || defined(_18F452)
// TRISE Register
static volatile near bit	IBF		@ ((unsigned)&TRISE*8)+7; //Input Buffer Full Flag
static volatile near bit	OBF		@ ((unsigned)&TRISE*8)+6; //Output Buffer Full Flag
static volatile near bit	IBOV		@ ((unsigned)&TRISE*8)+5; //Input Buffer Overflow Detect
static volatile near bit	PSPMODE		@ ((unsigned)&TRISE*8)+4; //Parallel Slave Port Select
static volatile near bit	TRISE2		@ ((unsigned)&TRISE*8)+2; //RE2 Direction Control Bit
static volatile near bit	TRISE1		@ ((unsigned)&TRISE*8)+1; //RE1 Direction Control Bit
static volatile near bit	TRISE0		@ ((unsigned)&TRISE*8)+0; //RE0 Direction Control Bit

// TRISD Register
static volatile near bit 	TRISD7	@ ((unsigned)&TRISD*8)+7;	// port D data direction
static volatile near bit 	TRISD6	@ ((unsigned)&TRISD*8)+6;
static volatile near bit 	TRISD5	@ ((unsigned)&TRISD*8)+5;
static volatile near bit 	TRISD4	@ ((unsigned)&TRISD*8)+4;
static volatile near bit 	TRISD3	@ ((unsigned)&TRISD*8)+3;
static volatile near bit 	TRISD2	@ ((unsigned)&TRISD*8)+2;
static volatile near bit 	TRISD1	@ ((unsigned)&TRISD*8)+1;
static volatile near bit 	TRISD0	@ ((unsigned)&TRISD*8)+0;
#endif

// TRISC Register
static volatile near bit 	TRISC7	@ ((unsigned)&TRISC*8)+7;	// port C data direction
static volatile near bit 	TRISC6	@ ((unsigned)&TRISC*8)+6;
static volatile near bit 	TRISC5	@ ((unsigned)&TRISC*8)+5;
static volatile near bit 	TRISC4	@ ((unsigned)&TRISC*8)+4;
static volatile near bit 	TRISC3	@ ((unsigned)&TRISC*8)+3;
static volatile near bit 	TRISC2	@ ((unsigned)&TRISC*8)+2;
static volatile near bit 	TRISC1	@ ((unsigned)&TRISC*8)+1;
static volatile near bit 	TRISC0	@ ((unsigned)&TRISC*8)+0;

// TRISB Register
static volatile near bit 	TRISB7	@ ((unsigned)&TRISB*8)+7;	// port B data direction
static volatile near bit 	TRISB6	@ ((unsigned)&TRISB*8)+6;
static volatile near bit 	TRISB5	@ ((unsigned)&TRISB*8)+5;
static volatile near bit 	TRISB4	@ ((unsigned)&TRISB*8)+4;
static volatile near bit 	TRISB3	@ ((unsigned)&TRISB*8)+3;
static volatile near bit 	TRISB2	@ ((unsigned)&TRISB*8)+2;
static volatile near bit 	TRISB1	@ ((unsigned)&TRISB*8)+1;
static volatile near bit 	TRISB0	@ ((unsigned)&TRISB*8)+0;

// TRISA Register
static volatile near bit 	TRISA6	@ ((unsigned)&TRISA*8)+6;	//Port A data direction Register
static volatile near bit 	TRISA5	@ ((unsigned)&TRISA*8)+5;
static volatile near bit 	TRISA4	@ ((unsigned)&TRISA*8)+4;
static volatile near bit 	TRISA3	@ ((unsigned)&TRISA*8)+3;
static volatile near bit 	TRISA2	@ ((unsigned)&TRISA*8)+2;
static volatile near bit 	TRISA1	@ ((unsigned)&TRISA*8)+1;
static volatile near bit 	TRISA0	@ ((unsigned)&TRISA*8)+0;

#if defined(_18F442) || defined(_18F452)
//Latch E LATE
static volatile	near bit	LE0		@ ((unsigned)&LATE*8)+0;
static volatile	near bit	LE1		@ ((unsigned)&LATE*8)+1;
static volatile	near bit	LE2		@ ((unsigned)&LATE*8)+2;
//Alternate definitions
static volatile	near bit	LATE0		@ ((unsigned)&LATE*8)+0;
static volatile	near bit	LATE1		@ ((unsigned)&LATE*8)+1;
static volatile	near bit	LATE2		@ ((unsigned)&LATE*8)+2;

//Latch D LATD
static volatile	near bit	LD0		@ ((unsigned)&LATD*8)+0;
static volatile	near bit	LD1		@ ((unsigned)&LATD*8)+1;
static volatile	near bit	LD2		@ ((unsigned)&LATD*8)+2;