pic18fxx2.h

首先pic和铁电24c02通讯

/*
 * pic18fxx2.h
 * header file for Microchip PIC controllers
 * 18F242
 * 18F252
 * 18F442
 * 18F452
 *
 */

static volatile near unsigned char	TOSU		@ 0xFFF;
static volatile near unsigned char	TOSH		@ 0xFFE;
static volatile near unsigned char	TOSL		@ 0xFFD;
static volatile near unsigned char	STKPTR		@ 0xFFC;
static volatile	near unsigned char	PCLATU		@ 0xFFB;
static volatile	near unsigned char	PCLATH		@ 0xFFA;
static volatile	near unsigned char	PCL		@ 0xFF9;
static volatile far  unsigned char *	TBLPTR		@ 0xFF6;
static volatile	near unsigned char	TBLPTRU		@ 0xFF8;
static volatile	near unsigned char	TBLPTRH		@ 0xFF7;
static volatile	near unsigned char	TBLPTRL		@ 0xFF6;
static volatile	near unsigned char	TABLAT		@ 0xFF5;
static volatile	near unsigned char	PRODH		@ 0xFF4;
static volatile	near unsigned char	PRODL		@ 0xFF3;
static volatile near unsigned char	INTCON		@ 0xFF2;
static 		near unsigned char	INTCON2		@ 0xFF1;
static volatile	near unsigned char	INTCON3		@ 0xFF0;
static volatile	near unsigned char	INDF0		@ 0xFEF;
static volatile	near unsigned char	POSTINC0	@ 0xFEE;
static volatile	near unsigned char	POSTDEC0	@ 0xFED;
static volatile	near unsigned char	PREINC0		@ 0xFEC;
static volatile	near unsigned char	PLUSW0		@ 0xFEB;
static volatile	near unsigned char	FSR0H		@ 0xFEA;
static volatile	near unsigned char	FSR0L		@ 0xFE9;
static volatile near unsigned char	WREG		@ 0xFE8;
static volatile	near unsigned char	INDF1		@ 0xFE7;
static volatile	near unsigned char	POSTINC1      	@ 0xFE6;
static volatile	near unsigned char	POSTDEC1	@ 0xFE5;
static volatile	near unsigned char	PREINC1		@ 0xFE4;
static volatile	near unsigned char	PLUSW1		@ 0xFE3;
static volatile	near unsigned char	FSR1H		@ 0xFE2;
static volatile	near unsigned char	FSR1L		@ 0xFE1;
static 		near unsigned char	BSR		@ 0xFE0;
static volatile	near unsigned char	INDF2		@ 0xFDF;
static volatile	near unsigned char	POSTINC2	@ 0xFDE;
static volatile	near unsigned char	POSTDEC2	@ 0xFDD;
static volatile	near unsigned char	PREINC2		@ 0xFDC;
static volatile	near unsigned char	PLUSW2		@ 0xFDB;
static volatile	near unsigned char	FSR2H		@ 0xFDA;
static volatile	near unsigned char	FSR2L		@ 0xFD9;
static volatile near unsigned char	STATUS		@ 0xFD8;
static volatile near unsigned int	TMR0		@ 0xFD6;
static volatile near unsigned char	TMR0H		@ 0xFD7;
static volatile near unsigned char	TMR0L		@ 0xFD6;
static 		near unsigned char	T0CON		@ 0xFD5;
static volatile near unsigned char	OSCCON		@ 0xFD3;
static volatile	near unsigned char	LVDCON		@ 0xFD2;
static		near unsigned char	WDTCON		@ 0xFD1;
static volatile near unsigned char	RCON		@ 0xFD0;
static volatile near unsigned int	TMR1		@ 0xFCE;
static volatile near unsigned char	TMR1H		@ 0xFCF;
static volatile near unsigned char	TMR1L		@ 0xFCE;
static		near unsigned char	T1CON		@ 0xFCD;
static volatile near unsigned char	TMR2		@ 0xFCC;
static volatile near unsigned char	PR2		@ 0xFCB;
static		near unsigned char	T2CON		@ 0xFCA;
static volatile near unsigned char	SSPBUF		@ 0xFC9;
static volatile near unsigned char	SSPADD		@ 0xFC8;
static volatile near unsigned char	SSPSTAT		@ 0xFC7;
static volatile near unsigned char	SSPCON1		@ 0xFC6;
static volatile near unsigned char	SSPCON2		@ 0xFC5;
static volatile near unsigned int	ADRES		@ 0xFC3;
static volatile near unsigned char	ADRESH		@ 0xFC4;
static volatile near unsigned char	ADRESL		@ 0xFC3;
static volatile near unsigned char	ADCON0		@ 0xFC2;
static		near unsigned char	ADCON1		@ 0xFC1;
static volatile near unsigned int	CCPR1		@ 0xFBE;
static volatile near unsigned char	CCPR1H		@ 0xFBF;
static volatile near unsigned char	CCPR1L		@ 0xFBE;
static volatile near unsigned char	CCP1CON		@ 0xFBD;
static volatile near unsigned int	CCPR2		@ 0xFBB;
static volatile near unsigned char	CCPR2H		@ 0xFBC;
static volatile near unsigned char	CCPR2L		@ 0xFBB;
static volatile near unsigned char	CCP2CON		@ 0xFBA;
static volatile near unsigned int	TMR3		@ 0xFB2;
static volatile near unsigned char	TMR3H		@ 0xFB3;
static volatile near unsigned char	TMR3L		@ 0xFB2;
static		near unsigned char	T3CON		@ 0xFB1;
static		near unsigned char	SPBRG		@ 0xFAF;
static volatile near unsigned char	RCREG		@ 0xFAE;
static volatile near unsigned char	TXREG		@ 0xFAD;
static volatile near unsigned char	TXSTA		@ 0xFAC;
static volatile near unsigned char	RCSTA		@ 0xFAB;
static volatile	near unsigned char	EEADR		@ 0xFA9;
static volatile	near unsigned char	EEDATA		@ 0xFA8;
static volatile	near unsigned char	EECON2		@ 0xFA7;
static volatile	near unsigned char	EECON1		@ 0xFA6;
static 		near unsigned char	IPR2		@ 0xFA2;
static volatile near unsigned char	PIR2		@ 0xFA1;
static 		near unsigned char	PIE2		@ 0xFA0;
static		near unsigned char	IPR1		@ 0xF9F;
static volatile near unsigned char	PIR1		@ 0xF9E;
static		near unsigned char	PIE1		@ 0xF9D;
static volatile near unsigned char	TRISC		@ 0xF94;
static volatile	near unsigned char	TRISB		@ 0xF93;
static volatile near unsigned char	TRISA		@ 0xF92;
static volatile near unsigned char	LATC		@ 0xF8B;
static volatile	near unsigned char	LATB		@ 0xF8A;
static volatile near unsigned char	LATA		@ 0xF89;
static volatile near unsigned char	PORTC		@ 0xF82;
static volatile near unsigned char	PORTB		@ 0xF81;
static volatile near unsigned char	PORTA		@ 0xF80;
#if defined(_18F442) || defined(_18F452)
static volatile near unsigned char	TRISE		@ 0xF96;
static volatile near unsigned char	TRISD		@ 0xF95;
static volatile near unsigned char	LATE		@ 0xF8D;
static volatile near unsigned char	LATD		@ 0xF8C;
static volatile near unsigned char	PORTE		@ 0xF84;
static volatile near unsigned char	PORTD		@ 0xF83;
#endif

/*Defining individual bits*/
/*	STATUS bits	*/
static volatile near bit		NEGATIVE	@ ((unsigned)&STATUS*8)+4;
static volatile near bit		OVERFLOW	@ ((unsigned)&STATUS*8)+3;
static volatile near bit		ZERO    	@ ((unsigned)&STATUS*8)+2;
static volatile near bit		DC      	@ ((unsigned)&STATUS*8)+1;
static volatile near bit		CARRY   	@ ((unsigned)&STATUS*8)+0;

//Stack Pointer Register
static volatile near bit		STKFUL		@ ((unsigned)&STKPTR*8)+7; //Overflow Flag
static volatile near bit		STKUNF	 	@ ((unsigned)&STKPTR*8)+6; //Underflow Flag
static volatile near bit		SP4	 	@ ((unsigned)&STKPTR*8)+4;
static volatile near bit		SP3	 	@ ((unsigned)&STKPTR*8)+3;
static volatile near bit		SP2	 	@ ((unsigned)&STKPTR*8)+2;
static volatile near bit		SP1	 	@ ((unsigned)&STKPTR*8)+1;
static volatile near bit		SP0	 	@ ((unsigned)&STKPTR*8)+0;

//Interupt Control INTCON
static 		near bit		GIE		@ ((unsigned)&INTCON*8)+7; //Global Interrupt Enable
static 		near bit		GIEH		@ ((unsigned)&INTCON*8)+7;
static 		near bit		PEIE		@ ((unsigned)&INTCON*8)+6;
static 		near bit		GIEL		@ ((unsigned)&INTCON*8)+6;
static 		near bit		TMR0IE		@ ((unsigned)&INTCON*8)+5; //TM0 Overflow Interrupt Enable
static 		near bit		INT0IE		@ ((unsigned)&INTCON*8)+4; //INT0 External Interrupt Enable
static 		near bit		RBIE		@ ((unsigned)&INTCON*8)+3; //RB Port change Interrupt enable
static volatile near bit		TMR0IF		@ ((unsigned)&INTCON*8)+2; //TM0 Timer Overflow Flag
static volatile near bit		INT0IF		@ ((unsigned)&INTCON*8)+1; //INT0 External Interrupt Flag 
static volatile near bit		RBIF		@ ((unsigned)&INTCON*8)+0; //RB Port change Flag
static volatile near bit		INT0F		@ ((unsigned)&INTCON*8)+1; //alternative definition
static volatile near bit		T0IF		@ ((unsigned)&INTCON*8)+2; //alternative definition

//Interrupt Control 2 INTCON2
static 		near bit		RBPU		@ ((unsigned)&INTCON2*8)+7; //Port B Pull-Up Enable
static 		near bit		INTEDG0		@ ((unsigned)&INTCON2*8)+6; //Edge select INT0
static 		near bit		INTEDG1		@ ((unsigned)&INTCON2*8)+5; //Edge select INT1
static 		near bit		INTEDG2		@ ((unsigned)&INTCON2*8)+4; //Edge select INT2
static 		near bit		TMR0IP		@ ((unsigned)&INTCON2*8)+2; //TM0 Overflow Interrupt Priority
static 		near bit		RBIP		@ ((unsigned)&INTCON2*8)+0; //RB Port change interrupt Priority
static 		near bit		T0IP		@ ((unsigned)&INTCON2*8)+2; //alternative definition

//Interrupt Control 3 INTCON3
static 		near bit		INT2IP		@ ((unsigned)&INTCON3*8)+7; //INT2 Interrupt Priority
static 		near bit		INT1IP		@ ((unsigned)&INTCON3*8)+6; //INT1 Interrupt Priority
static 		near bit		INT2IE		@ ((unsigned)&INTCON3*8)+4; //Enable Interrupt INT2
static 		near bit		INT1IE		@ ((unsigned)&INTCON3*8)+3; //Enable Interrupt INT1
static volatile	near bit		INT2IF		@ ((unsigned)&INTCON3*8)+1; //INT2 Interrupt Flag
static volatile	near bit		INT1IF		@ ((unsigned)&INTCON3*8)+0; //INT1 Interrupt Flag

//Timer 0 Control T0CON
static 		near bit		TMR0ON		@ ((unsigned)&T0CON*8)+7; //TM0 on/off
static 		near bit		T08BIT		@ ((unsigned)&T0CON*8)+6; //TM0 8/16 Bit
static 		near bit		T0CS		@ ((unsigned)&T0CON*8)+5; //TM0 Clock Source Select
static 		near bit		T0SE		@ ((unsigned)&T0CON*8)+4; //TM0 Clock Edge Select
static 		near bit		PSA 		@ ((unsigned)&T0CON*8)+3; //TM0 Prescaler Arangement
static 		near bit		T0PS2 		@ ((unsigned)&T0CON*8)+2; //TM0 Prescale
static 		near bit		T0PS1 		@ ((unsigned)&T0CON*8)+1;
static 		near bit		T0PS0 		@ ((unsigned)&T0CON*8)+0;

//Oscillator Control OSCON
static 		near bit		SCS   		@ ((unsigned)&OSCCON*8)+0; //System Clock Switch

//Low Voltage Detect Control LVDCON
static volatile near bit		IRVST  		@ ((unsigned)&LVDCON*8)+5; //Internal Voltage ref. Stable Flag
static 		near bit		LVDEN  		@ ((unsigned)&LVDCON*8)+4; //Low Voltage Detect Enable
static 		near bit		LVV3   		@ ((unsigned)&LVDCON*8)+3; //Low Voltage Detection Limit Bits
static 		near bit		LVV2   		@ ((unsigned)&LVDCON*8)+2;
static 		near bit		LVV1   		@ ((unsigned)&LVDCON*8)+1;
static 		near bit		LVV0   		@ ((unsigned)&LVDCON*8)+0;

//Watchdog Control WDTCON
static 		near bit		SWDTEN 		@ ((unsigned)&WDTCON*8)+0; //Software Watchdog Timer Enable

//Reset Control register RCON
static		near bit 		IPEN  		@ ((unsigned)&RCON*8)+7; //Interrupt Priority Enable
static volatile near bit 		RI  		@ ((unsigned)&RCON*8)+4; //RESET instruction Flag Bit
static volatile near bit 		TO   		@ ((unsigned)&RCON*8)+3; //Watchdog Time Out Flag
static volatile near bit 		PD   		@ ((unsigned)&RCON*8)+2; //Power Down Detect Flag
static volatile near bit 		POR  		@ ((unsigned)&RCON*8)+1; //Power On Reset Staus
static volatile near bit		BOR  		@ ((unsigned)&RCON*8)+0; //Brown Out Reset Staus

//Timer 1 Control T1CON
static		near bit		RD16		@ ((unsigned)&T1CON*8)+7;	// 16 Bit Read/Write Enable
static		near bit		T1RD16 		@ ((unsigned)&T1CON*8)+7; //16 Bit Read write mode
static		near bit		T1CKPS1		@ ((unsigned)&T1CON*8)+5; //TM1 Clock input prescale
static		near bit		T1CKPS0		@ ((unsigned)&T1CON*8)+4; //
static		near bit		T1OSCEN		@ ((unsigned)&T1CON*8)+3; //TM1 Oscillator Enable
static		near bit		T1SYNC 		@ ((unsigned)&T1CON*8)+2; //TM1 Ext. Clock Synchronize select
static		near bit		TMR1CS 		@ ((unsigned)&T1CON*8)+1; //TM1 Clock Source Select
static		near bit		TMR1ON 		@ ((unsigned)&T1CON*8)+0; //TM1 Enable/Stop

//Timer 2 Control T2CON
static		near bit		TOUTPS3		@ ((unsigned)&T2CON*8)+6; //TM2 Output Postscale
static		near bit		TOUTPS2		@ ((unsigned)&T2CON*8)+5; //
static		near bit		TOUTPS1		@ ((unsigned)&T2CON*8)+4; //
static		near bit		TOUTPS0		@ ((unsigned)&T2CON*8)+3; //
static		near bit		TMR2ON		@ ((unsigned)&T2CON*8)+2; //TM2 Enable/Stop
static		near bit		T2CKPS1		@ ((unsigned)&T2CON*8)+1; //TM2 Clock Prescale
static		near bit		T2CKPS0		@ ((unsigned)&T2CON*8)+0; //