altmemddr_phy_alt_mem_phy_pll_ciii.v
来自「nios里面用自定义指令集来实现三角函数」· Verilog 代码 · 共 482 行 · 第 1/2 页
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altmemddr_phy_alt_mem_phy_pll_ciii.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 175 11/20/2007 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altmemddr_phy_alt_mem_phy_pll_ciii (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
locked,
phasedone);
input areset;
input inclk0;
input [2:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output locked;
output phasedone;
wire [4:0] sub_wire0;
wire sub_wire6;
wire sub_wire7;
wire [0:0] sub_wire10 = 1'h0;
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire c4 = sub_wire5;
wire locked = sub_wire6;
wire phasedone = sub_wire7;
wire sub_wire8 = inclk0;
wire [1:0] sub_wire9 = {sub_wire10, sub_wire8};
altpll altpll_component (
.phasestep (phasestep),
.phaseupdown (phaseupdown),
.inclk (sub_wire9),
.phasecounterselect (phasecounterselect),
.areset (areset),
.scanclk (scanclk),
.clk (sub_wire0),
.locked (sub_wire6),
.phasedone (sub_wire7),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.charge_pump_current_bits = 1,
altpll_component.compensate_clock = "CLK1",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.loop_filter_c_bits = 0,
altpll_component.loop_filter_r_bits = 27,
altpll_component.lpm_type = "altpll",
altpll_component.m = 22,
altpll_component.m_initial = 3,
altpll_component.m_ph = 4,
altpll_component.n = 1,
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Fast",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 113,
altpll_component.vco_post_scale = 1,
altpll_component.width_clock = 5,
altpll_component.width_phasecounterselect = 3,
altpll_component.c0_high = 10,
altpll_component.c0_initial = 3,
altpll_component.c0_low = 10,
altpll_component.c0_mode = "even",
altpll_component.c0_ph = 4,
altpll_component.c1_high = 5,
altpll_component.c1_initial = 3,
altpll_component.c1_low = 5,
altpll_component.c1_mode = "even",
altpll_component.c1_ph = 4,
altpll_component.c2_high = 5,
altpll_component.c2_initial = 1,
altpll_component.c2_low = 5,
altpll_component.c2_mode = "even",
altpll_component.c2_ph = 0,
altpll_component.c3_high = 5,
altpll_component.c3_initial = 3,
altpll_component.c3_low = 5,
altpll_component.c3_mode = "even",
altpll_component.c3_ph = 4,
altpll_component.c4_high = 5,
altpll_component.c4_initial = 3,
altpll_component.c4_low = 5,
altpll_component.c4_mode = "even",
altpll_component.c4_ph = 4,
altpll_component.clk0_counter = "c0",
altpll_component.clk1_counter = "c1",
altpll_component.clk2_counter = "c2",
altpll_component.clk3_counter = "c3",
altpll_component.clk4_counter = "c4";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
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