altmemddr_phy_ddr_pins.tcl

来自「nios里面用自定义指令集来实现三角函数」· TCL 代码 · 共 968 行 · 第 1/3 页

# Same as get_clock_latency, but returns the clock phase (0<=x<360) normalised instead
proc get_clock_phase {period clockname risefall } {
	set countclocks 0
	if { $risefall != "rise" && $risefall != "fall" } {
		error "Internal error: get_clock_phase risefall was $risefall expected \"rise\" or \"fall\""
	}
	foreach_in_collection c [get_clocks $clockname] { 
		set clock $c
		incr countclocks
	}
	if { $countclocks == 1 } {
		if { $risefall == "rise" } {
			set offset 0
		} elseif { $risefall == "fall" } {
			set offset 180
		} else {
			error "Unreachable in get_clock_phase"
		}
	} else {
		error "Internal error: Found $countclocks matching $clockname. Expected 1 in get_clock_phase"
	}
	set phase [get_clock_info -phase $clock]
	set res [expr {fmod(($phase+$offset+360),360)}]
	return $res
}


proc expr_debug { exp } {
	upvar expr_debug_e expr_debug_e
	set expr_debug_e $exp
	uplevel {
	puts "-----------------"
	puts "[regsub -all {[\n \t]+} $expr_debug_e " "]"
	puts "-----------------"
	puts [regsub -all {[\n \t]+} [subst $expr_debug_e] " "]
	puts "-----------------"
	set expr_debug_temp [expr $expr_debug_e]
	puts "=$expr_debug_temp" 
	puts "-----------------"
	return $expr_debug_temp
	}
}

# Return all the ck output clocks in the current design of a given type and 
# inversion
# type - either tDSS/tDQSS/ac_rise/ac_fall
# pn - either p/n
proc get_output_clocks {type pn} {
	global ck_output_clocks
	return $ck_output_clocks(${type}-${pn})
}

proc add_output_clock {type pn clockname} {
	global ck_output_clocks
	if { ! [info exists ck_output_clocks(${type}-${pn})] } {
		set ck_output_clocks(${type}-${pn}) [list]
	} 
	lappend ck_output_clocks(${type}-${pn}) $clockname
}

# ----------------------------------------------------------------
#
proc get_timequest_name {hier_name} {
#
# Description:  Convert the full hierarchy name into a TimeQuest name
#
# ----------------------------------------------------------------
	set sta_name ""
	for {set inst_start [string first ":" $hier_name]} {$inst_start != -1} {set inst_start [string first ":" $hier_name $inst_start]} {
		incr inst_start
		set inst_end [string first "|" $hier_name $inst_start]
		if {$inst_end == -1} {
			append sta_name [string range $hier_name $inst_start end]
		} else {
			append sta_name [string range $hier_name $inst_start $inst_end]
		}
	}
	return $sta_name
}

# ----------------------------------------------------------------
#
proc get_core_instance_list {corename} {
#
# Description:  Get a list of all ALTMEMPHY instances in TimeQuest
#
# ----------------------------------------------------------------
	set full_instance_list [get_core_full_instance_list $corename]
	set instance_list [list]

	foreach inst $full_instance_list {
		set sta_name [get_timequest_name $inst]
		if {[lsearch $instance_list $sta_name] == -1} {
			lappend instance_list $sta_name
		}
	}
	return $instance_list
}

# ----------------------------------------------------------------
#
proc get_core_full_instance_list {corename} {
#
# Description:  Get a list of all ALTMEMPHY instances (full hierarchy names)
#               in TimeQuest
#
# ----------------------------------------------------------------
	set instance_list [list]

	# Look for a keeper (register) name
	# Try mem_clk[0] to determine core instances
	set search_list [list "*"]
	set found 0
	for {set i 0} {$found == 0 && $i != [llength $search_list]} {incr i} {
		set pattern [lindex $search_list $i]
		set instance_collection [get_keepers "*|${corename}:*|$pattern"]
		if {[get_collection_size $instance_collection] == 0} {
			set instance_collection [get_keepers "${corename}:*|$pattern"]
		}
		if {[get_collection_size $instance_collection] > 0} {
			set found 1
		}
	}
	# regexp to extract the full hierarchy path of an instance name
	set inst_regexp {(^.*}
	append inst_regexp ${corename}
	append inst_regexp {:[A-Za-z0-9\.\\_\[\]\-\$()]+)\|}
	foreach_in_collection inst $instance_collection {
		set name [get_node_info -name $inst]
		if {[regexp -- $inst_regexp $name -> hier_name] == 1} {
			if {[lsearch $instance_list $hier_name] == -1} {
				lappend instance_list $hier_name
			}
		}
	}
	return $instance_list
}

# ----------------------------------------------------------------
#
proc traverse_fanin_up_to_depth { node_id match_command edge_type results_array_name depth} {
#
# Description: Recurses through the timing netlist starting from the given
#              node_id through edges of type edge_type to find nodes
#              satisfying match_command.
#              Recursion depth is bound to the specified depth.
#              Adds the resulting TDB node ids to the results_array.
#
# ----------------------------------------------------------------
	upvar 1 $results_array_name results

	if {$depth < 0} {
		error "Internal error: Bad timing netlist search depth"
	}
	set fanin_edges [get_node_info -${edge_type}_edges $node_id]
	set number_of_fanin_edges [llength $fanin_edges]
	for {set i 0} {$i != $number_of_fanin_edges} {incr i} {
		set fanin_edge [lindex $fanin_edges $i]
		set fanin_id [get_edge_info -src $fanin_edge]
		if {$match_command == "" || [eval $match_command $fanin_id] != 0} {
			set results($fanin_id) 1
		} elseif {$depth == 0} {
			# Max recursion depth
		} else {
			traverse_fanin_up_to_depth $fanin_id $match_command $edge_type results [expr "$depth - 1"]
		}
	}
}

# ----------------------------------------------------------------
#
proc is_node_type_pll_inclk { node_id } {
#
# Description: Given a node, tells whether or not it is a PLL clk
#
# ----------------------------------------------------------------
	set cell_id [get_node_info -cell $node_id]
	set atom_type [get_cell_info -atom_type $cell_id]
	if {$atom_type == "PLL"} {
		set node_name [get_node_info -name $node_id]
		set fanin_edges [get_node_info -clock_edges $node_id]
		# The inclk input should have a |inclk or |inclk[0] suffix
		if {([string match "*|inclk" $node_name] || [string match "*|inclk\\\[0\\\]" $node_name]) && [llength $fanin_edges] > 0} {
			set result 1
		} else {
			set result 0
		}
	} else {
		set result 0
	}

	return $result
}

# ----------------------------------------------------------------
#
proc is_node_type_pin { node_id } {
#
# Description: Given a node, tells whether or not it is a reg
#
# ----------------------------------------------------------------
	set node_type [get_node_info -type $node_id]
	if {$node_type == "port"} {
		set result 1
	} else {
		set result 0
	}
	return $result
}

# ----------------------------------------------------------------
#
proc get_input_clk_id { pll_output_node_id } {
#
# Description: Given a PLL clock output node, gets the PLL clock input node
#
# ----------------------------------------------------------------
	if {[is_node_type_pll_clk $pll_output_node_id]} {
		array set results_array [list]
		traverse_fanin_up_to_depth $pll_output_node_id is_node_type_pll_inclk clock results_array 1
		if {[array size results_array] == 1} {
			set pll_inclk_id [lindex [array names results_array] 0]
			array unset results_array
			traverse_fanin_up_to_depth $pll_inclk_id is_node_type_pin clock results_array 5
			if {[array size results_array] == 1} {
				set pin_id [lindex [array names results_array] 0]
				set result $pin_id
			} else {
				post_message -type critical_warning "Could not find dedicated PLL input pin for [get_node_info -name $pll_output_node_id]"
				set result ""
			}
		} else {
			post_message -type critical_warning "Could not find PLL clock for [get_node_info -name $pll_output_node_id]"
			set result ""
		}
	} else {
		error "Internal error: get_input_clk_id only works on PLL output clocks"
	}
	return $result
}

# ----------------------------------------------------------------
#
proc is_node_type_pll_clk { node_id } {
#
# Description: Given a node, tells whether or not it is a PLL clk
#
# ----------------------------------------------------------------
	set cell_id [get_node_info -cell $node_id]
	set atom_type [get_cell_info -atom_type $cell_id]
	if {$atom_type == "PLL"} {
		set node_name [get_node_info -name $node_id]
		if {[string match "*|clk\\\[*\\\]" $node_name]} {
			set result 1
		} else {
			set result 0
		}
	} else {
		set result 0
	}

	return $result
}

# ----------------------------------------------------------------
#
proc get_pll_clock { dest_id_list node_type clock_id_name search_depth} {
#
# Description: Look for the PLL output clocking the given nodes
#
# ----------------------------------------------------------------
	if {$clock_id_name != ""} {
		upvar 1 $clock_id_name clock_id
	}
	set clock_id -1

	array set clk_array [list]
	foreach node_id $dest_id_list {
		traverse_fanin_up_to_depth $node_id is_node_type_pll_clk clock clk_array $search_depth
	}
	if {[array size clk_array] == 1} {
		set clock_id [lindex [array names clk_array] 0]
		set clk [get_node_info -name $clock_id]
	} elseif {[array size clk_array] > 1} {
		puts "Found more than 1 clock driving the $node_type"
		set clk ""
	} else {
		set clk ""
		#puts "Could not find $node_type clock"
	}

	return $clk
}

# ----------------------------------------------------------------
#
proc get_output_clock_id { ddio_output_pin_list pin_type msg_list_name {max_search_depth 13} } {
#
# Description: Look for the PLL output clocks of the given pins
#
# ----------------------------------------------------------------
	upvar 1 $msg_list_name msg_list
	set output_clock_id -1
	
	set output_id_list [list]
	set pin_collection [get_keepers $ddio_output_pin_list]
	if {[get_collection_size $pin_collection] == [llength $ddio_output_pin_list]} {
		foreach_in_collection id $pin_collection {
			lappend output_id_list $id
		}
	} elseif {[get_collection_size $pin_collection] == 0} {
		lappend msg_list "warning" "Could not find any $pin_type pins"
	} else {
		lappend msg_list "warning" "Could not find all $pin_type pins"
	}
	get_pll_clock $output_id_list $pin_type output_clock_id $max_search_depth
	return $output_clock_id
}

# ----------------------------------------------------------------
#
proc is_node_type_io_clock_divider_clkout { node_id } {
#