altmemddr_phy_ddr_pins.tcl

来自「nios里面用自定义指令集来实现三角函数」· TCL 代码 · 共 968 行 · 第 1/3 页

# This is a library of useful functions to include at the top of an SDC file.

proc walk_to_pin {type mainnode {depth 10}} {
	if { $type == "fanout" } {
		set edgename "-fanout_edges"
		set srcdst "-dst"
	} elseif { $type == "clock" } {
		set edgename "-clock_edges"
		set srcdst "-src"
	} elseif { $type == "fanin" } {
		set edgename "-synch_edges"
		set srcdst "-src"
	}
	set fanout [get_node_info $edgename $mainnode]
	foreach edge $fanout {
		set node [get_edge_info $srcdst $edge]
		if { [get_node_info -type $node] == "port" } {
			return $node
		}
		if {$depth > 0 &&  [get_node_info -type $node] == "comb"} {
			#puts "walking down [get_node_info -name $node] [get_node_info -type $node]..."
			set res [walk_to_pin $type $node [expr {$depth - 1}]]
			if { $res != "" } {
				return $res
			}
		} else {
			#puts "ignoring node [get_node_info -name $node] of type [get_node_info -type $node]"
		}
	}
	return ""
}

# Like walk_to_pin, but searches out in a tree if the 
# pin drives multiple ports
proc walk_to_all_pins {type collection {depth 10}} {
	if { $type == "fanout" } {
		set edgename "-fanout_edges"
		set srcdst "-dst"
	} elseif { $type == "clock" } {
		set edgename "-clock_edges"
		set srcdst "-src"
	} elseif { $type == "fanin" } {
		set edgename "-synch_edges"
		set srcdst "-src"
	}
	set res [list]
	foreach_in_collection mainnode $collection {
		set fanout [get_node_info $edgename $mainnode]
		foreach edge $fanout {
			set node [get_edge_info $srcdst $edge]
			if { [get_node_info -type $node] == "port" } {
				lappend res $node
			}
			if {$depth > 0 &&  [get_node_info -type $node] == "comb"} {
				#puts "walking down [get_node_info -name $node] [get_node_info -type $node]..."
				set r [walk_to_pin $type $node [expr {$depth - 1}]]
				set res [concat $res $r] 
			} else {
				#puts "ignoring node [get_node_info -name $node] of type [get_node_info -type $node]"
			}
		}
	}
	return $res
}


# (map walk_to_pin)
proc walk_to_pins { type collection {depth 10} } {
	set res [list]
	foreach_in_collection c $collection {
		set i [walk_to_pin $type $c $depth]
		if { $i == "" } {
			#puts "Node [get_node_info -name $c] was a dead end"
		} else {
			#puts "Got port for node [get_node_info -name $c]"
			lappend res $i
		}
	}
	#puts "walk_to_pins returning: $res"
	return $res
}

# (map get_node_info -name)
proc map_get_node_name {nodes} {
	set res [list]
	foreach n $nodes {
		lappend res [get_node_info -name $n]
	}
	return $res
}

proc get_all_dqs_pins { dqsgroups} { 
	set res [list]
	foreach dqsgroup $dqsgroups {
		lappend res [lindex $dqsgroup 0]
	}
	return $res
}

proc get_all_dq_pins { dqsgroups} { 
	set res [list]
	foreach dqsgroup $dqsgroups {
		set res [concat $res [lindex $dqsgroup 2]]
	}
	return $res
}

proc get_all_dm_pins { dqsgroups} { 
	set res [list]
	foreach dqsgroup $dqsgroups {
		set res [concat $res [lindex $dqsgroup 1]]
	}
	return $res
}


proc list_collection { col } {
	set res "("
	foreach_in_collection c $col {
		append res "[get_node_info -name $c]\n"
	}
	append res ")"
	return $res
}

proc sett_collection { vlist col } {
	set i 0
	set len [llength $vlist]
	foreach_in_collection c $col {
		if { $i < $len } {
			upvar 1 [lindex $vlist $i] x
			set x $c
			incr i
		} else {
			error "Too many items in collection ([expr {$i+1}]) for list $vlist"
		}
	}
	if { $i != $len } {
		error "Too Few items in collection ($i) for list $vlist"
	}
}

# Return a tuple of the tCCS value for a given device
proc get_tccs { mem_if_memtype dqs_list period } {
	global TimeQuestInfo
	set family $TimeQuestInfo(family)
	set interface_type [get_io_interface_type $dqs_list]
	# The tCCS for a HYBRID interface is the same as a HPAD interface
	if {$interface_type == "HYBRID"} {
		set interface_type "HPAD"
	}
	set io_std [get_io_standard [lindex $dqs_list 0]]
  	set result [list 0 0]
	if {$interface_type != "" && $interface_type != "UNKNOWN" && $io_std != "" && $io_std != "UNKNOWN"} {
		package require ::quartus::ddr_timing_model
		if {[catch {get_io_standard_node_delay -dst TCCS_LEAD -io_standard $io_std -parameters [list IO $interface_type]} tccs_lead] != 0 || $tccs_lead == "" || $tccs_lead == 0 || \
				[catch {get_io_standard_node_delay -dst TCCS_LAG -io_standard $io_std -parameters [list IO $interface_type]} tccs_lag] != 0 || $tccs_lag == "" || $tccs_lag == 0 } {
			puts "Using Default Timing Model for tCCS of $io_std $interface_type"
		} else {
			puts "Using Quartus DDR Timing Model for tCCS $tccs_lead $tccs_lag"
			return [list $tccs_lead $tccs_lag]
		}
	}
	set speed_grade $TimeQuestInfo(speed_grade)
	set f "$io_std/$interface_type/$family/$speed_grade"
	switch -glob $f {
		"SSTL_18_*/VPAD/Cyclone III/6"  { return [list 585 585] }
		"SSTL_2_*/VPAD/Cyclone III/6"  { return [list 610 610] }
		"HSTL_*/VPAD/Cyclone III/6"  { return [list 670 670] }
		"SSTL_18_*/VPAD/Cyclone III/7"  { return [list 595 595] }
		"SSTL_2_*/VPAD/Cyclone III/7"  { return [list 620 620] }
		"HSTL_*/VPAD/Cyclone III/7"  { return [list 675 675] }
		"SSTL_18_*/VPAD/Cyclone III/8"  { return [list 595 595] }
		"SSTL_2_*/VPAD/Cyclone III/8"  { return [list 630 630] }
		"HSTL_*/VPAD/Cyclone III/8"  { return [list 685 685] }

		"SSTL_18_*/HPAD/Cyclone III/6"  { return [list 645 645] }
		"SSTL_2_*/HPAD/Cyclone III/6"  { return [list 670 670] }
		"HSTL_*/HPAD/Cyclone III/6"  { return [list 725 725] }
		"SSTL_18_*/HPAD/Cyclone III/7"  { return [list 650 650] }
		"SSTL_2_*/HPAD/Cyclone III/7"  { return [list 680 680] }
		"HSTL_*/HPAD/Cyclone III/7"  { return [list 735 735] }
		"SSTL_18_*/HPAD/Cyclone III/8"  { return [list 660 660] }
		"SSTL_2_*/HPAD/Cyclone III/8"  { return [list 685 685] }
		"HSTL_*/HPAD/Cyclone III/8"  { return [list 740 740] }

		"SSTL_18_*/HYBRID/Cyclone III/6"  { return [list 645 645] }
		"SSTL_2_*/HYBRID/Cyclone III/6"  { return [list 670 670] }
		"HSTL_*/HYBRID/Cyclone III/6"  { return [list 725 725] }
		"SSTL_18_*/HYBRID/Cyclone III/7"  { return [list 650 650] }
		"SSTL_2_*/HYBRID/Cyclone III/7"  { return [list 680 680] }
		"HSTL_*/HYBRID/Cyclone III/7"  { return [list 735 735] }
		"SSTL_18_*/HYBRID/Cyclone III/8"  { return [list 660 660] }
		"SSTL_2_*/HYBRID/Cyclone III/8"  { return [list 685 685] }
		"HSTL_*/HYBRID/Cyclone III/8"  { return [list 740 740] }

		"*SSTL_*/VPAD/Stratix III/2"  { return [list 267 267] }
		"*SSTL_*/VPAD/Stratix III/3"  { return [list 321 321] }
		"*SSTL_*/VPAD/Stratix III/4*"  { return [list 400 400] }
		"*HSTL_*/VPAD/Stratix III/2"  { return [list 277 277] }
		"*HSTL_*/VPAD/Stratix III/3"  { return [list 323 323] }
		"*HSTL_*/VPAD/Stratix III/4*"  { return [list 388 388] }

		"*SSTL_*/HPAD/Stratix III/2"  { return [list 267 267] }
		"*SSTL_*/HPAD/Stratix III/3"  { return [list 321 321] }
		"*SSTL_*/HPAD/Stratix III/4*"  { return [list 400 400] }
		"*HSTL_*/HPAD/Stratix III/2"  { return [list 277 277] }
		"*HSTL_*/HPAD/Stratix III/3"  { return [list 333 333] }
		"*HSTL_*/HPAD/Stratix III/4*"  { return [list 416 416] }

		default { error "Can't recognise mem_if_memtype/family/speed grade combination $f"}
	}
}

# Return a tuple of setup,hold time for read capture
proc get_tsw { mem_if_memtype dqs_list period} {
	global TimeQuestInfo
	set family $TimeQuestInfo(family)
	set interface_type [get_io_interface_type $dqs_list]
	set io_std [get_io_standard [lindex $dqs_list 0]]
	if {$interface_type != "" && $interface_type != "UNKNOWN" && $io_std != "" && $io_std != "UNKNOWN"} {
		package require ::quartus::ddr_timing_model
		if {[catch {get_io_standard_node_delay -dst TSU -io_standard $io_std -parameters [list IO $interface_type]} tsw_setup] != 0 || $tsw_setup == "" || $tsw_setup == 0 || \
				[catch {get_io_standard_node_delay -dst TH -io_standard $io_std -parameters [list IO $interface_type]} tsw_hold] != 0 || $tsw_hold == "" || $tsw_hold == 0 } {
			puts "Using Default Timing Model for tSW of $io_std $interface_type"
		} else {
			puts "Using Quartus DDR Timing Model for tSW $tsw_setup $tsw_hold"
			return [list $tsw_setup $tsw_hold]
		}
	}
	set speed_grade $TimeQuestInfo(speed_grade)
	set f "$io_std/$interface_type/$family/$speed_grade"
	switch -glob $f {
		"SSTL_18_*/HYBRID/Cyclone III/6"  { return [list [expr 745 745]] }
		"SSTL_2_*/HYBRID/Cyclone III/6"  { return [list [expr 730 730]] }
		"HSTL_*/HYBRID/Cyclone III/6"  { return [list [expr 780 780]] }
		"SSTL_18_*/HYBRID/Cyclone III/7"  { return [list [expr 840 840]] }
		"SSTL_2_*/HYBRID/Cyclone III/7"  { return [list [expr 843 843]] }
		"HSTL_*/HYBRID/Cyclone III/7"  { return [list [expr 885 885]] }
		"SSTL_18_*/HYBRID/Cyclone III/8"  { return [list [expr 945 945]] }
		"SSTL_2_*/HYBRID/Cyclone III/8"  { return [list [expr 975 975]] }
		"HSTL_*/HYBRID/Cyclone III/8"  { return [list [expr 970 970]] }

		"*SSTL_*/VPAD/Stratix III/2"  { return [list 250 250] }
		"*SSTL_*/VPAD/Stratix III/3"  { return [list 300 300] }
		"*SSTL_*/VPAD/Stratix III/4*"  { return [list 374 374] }
		"HSTL_*/VPAD/Stratix III/2"  { return [list 260 260] }
		"HSTL_*/VPAD/Stratix III/3"  { return [list 303 303] }
		"HSTL_*/VPAD/Stratix III/4*"  { return [list 364 364] }

		"*SSTL_18_*/HPAD/Stratix III/2"  { return [list 250 250] }
		"*SSTL_18_*/HPAD/Stratix III/3"  { return [list 280 280] }
		"*SSTL_18_*/HPAD/Stratix III/4*"  { return [list 375 375] }
		"*SSTL_15_*/HPAD/Stratix III/2"  { return [list 250 250] }
		"*SSTL_15_*/HPAD/Stratix III/3"  { return [list 300 300] }
		"*SSTL_15_*/HPAD/Stratix III/4*"  { return [list 374 374] }
		"*SSTL_2_*/HPAD/Stratix III/2"  { return [list 250 250] }
		"*SSTL_2_*/HPAD/Stratix III/3"  { return [list 300 300] }
		"*SSTL_2_*/HPAD/Stratix III/4*"  { return [list 374 374] }
		"HSTL_*/HPAD/Stratix III/2"  { return [list 260 260] }
		"HSTL_*/HPAD/Stratix III/3"  { return [list 312 312] }
		"HSTL_*/HPAD/Stratix III/4*"  { return [list 390 390] }
		default { error "Can't recognise io_std/interface_type/family/speed grade combination $f"}
	}
}

proc round_3dp { x } {
	return [expr { round($x * 1000) / 1000.0  } ]
}

proc min { a b } {
	if { $a == "" } { 
		return $b
	} elseif { $a < $b } {
		return $a
	} else {
		return $b
	}
}

proc max { a b } {
	if { $a == "" } { 
		return $b
	} elseif { $a > $b } {
		return $a
	} else {
		return $b
	}
}

proc wrap_to_period {period t} {
	return [expr {fmod(fmod($t,$period) + $period,$period)}]
}

proc get_clock_latency {period clockname risefall } {
	set countclocks 0
	if { $risefall != "rise" && $risefall != "fall" } {
		error "Internal error: get_clock_latency risefall was $risefall expected \"rise\" or \"fall\""
	}
	foreach_in_collection c [get_clocks $clockname] { 
		set clock $c
		incr countclocks
	}
	if { $countclocks == 1 } {
		if { $risefall == "rise" } {
			set edge_index 0
		} elseif { $risefall == "fall" } {
			set edge_index 1
		} else {
			error "Unreachable in get_clock_latency"
		}
	} else {
		error "Internal error: Found $countclocks matching $clockname. Expected 1 in get_clock_latency"
	}
	set waveform [get_clock_info -waveform $clock]
	if {[llength $waveform] != 2 } {
		error "Internal error: Waveform for clock $clockname is \"$waveform\""
	}
	set latency [lindex $waveform $edge_index]
	set res [wrap_to_period $period $latency]
	return $res
}