cycloneiii_3c25_start_niosii_standard_sopc.sopc

nios里面用自定义指令集来实现三角函数

      }
   }
   element osc_clk
   {
   }
   element pipeline_bridge_peripherals.s1
   {
      datum baseAddress
      {
         value = "134217728";
         type = "long";
      }
   }
}
</parameter>
    <parameter valueString="false" name="hardcopyCompatible"/>
    <parameter valueString="CYCLONEIII" name="deviceFamily"/>
    <parameter valueString="false" name="generateLegacySim"/>
    <parameter name="projectName">cycloneIII_3c25_start_niosII_standard.qpf</parameter>
    <parameter valueString="VERILOG" name="hdlLanguage"/>
    <parameter name="projectDirectory">C:\work\rod_designs\alu_nios2_dpfp\fpu_hw_3c25_standard</parameter>
    <module version="7.2" name="osc_clk" kind="clock_source">
        <parameter valueString="true" name="clockFrequencyKnown"/>
        <parameter valueString="50000000" name="clockFrequency"/>
    </module>
    <module version="7.2" name="cpu" kind="altera_nios2">
        <parameter valueString="" name="userDefinedSettings"/>
        <parameter valueString="Automatic" name="setting_branchPredictionType"/>
        <parameter valueString="_10" name="mmu_processIDNumBits"/>
        <parameter valueString="32" name="exceptionOffset"/>
        <parameter valueString="EmbeddedMulFast" name="muldiv_multiplierType"/>
        <parameter valueString="_4096" name="icache_size"/>
        <parameter valueString="_128" name="debug_OCIOnchipTrace"/>
        <parameter valueString="Fast" name="impl"/>
        <parameter valueString="_4" name="mmu_uitlbNumEntries"/>
        <parameter valueString="onchip_ram.s1" name="exceptionSlave"/>
        <parameter valueString="false" name="dcache_omitDataMaster"/>
        <parameter valueString="0" name="mmu_TLBMissExcOffset"/>
        <parameter valueString="false" name="setting_illegalMemAccessDetection"/>
        <parameter valueString="32" name="breakOffset"/>
        <parameter valueString="true" name="debug_embeddedPLL"/>
        <parameter valueString="false" name="setting_debugSimGen"/>
        <parameter valueString="false" name="setting_alwaysBypassDCache"/>
        <parameter valueString="_1" name="icache_numTCIM"/>
        <parameter valueString="false" name="setting_showInternalSettings"/>
        <parameter valueString="false" name="setting_illegalInstructionsTrap"/>
        <parameter valueString="0" name="resetOffset"/>
        <parameter valueString="false" name="setting_bhtIndexPcOnly"/>
        <parameter valueString="true" name="setting_HDLSimCachesCleared"/>
        <parameter valueString="true" name="setting_alwaysEncrypt"/>
        <parameter valueString="false" name="setting_activateModelChecker"/>
        <parameter valueString="_32" name="dcache_lineSize"/>
        <parameter valueString="false" name="setting_allowFullAddressRange"/>
        <parameter valueString="_7" name="mmu_dtlbPtrSz"/>
        <parameter valueString="_4" name="mmu_itlbNumWays"/>
        <parameter valueString="false" name="setting_avalonDebugPortPresent"/>
        <parameter valueString="false" name="cpuReset"/>
        <parameter valueString="true" name="setting_clearXBitsLDNonBypass"/>
        <parameter valueString="_4" name="mmu_dtlbNumWays"/>
        <parameter valueString="ext_flash.s1" name="resetSlave"/>
        <parameter valueString="_32" name="setting_perfCounterWidth"/>
        <parameter valueString="" name="mmu_TLBMissExcSlave"/>
        <parameter name="breakSlave">cpu.jtag_debug_module</parameter>
        <parameter valueString="false" name="setting_preciseIllegalMemAccessException"/>
        <parameter valueString="Level1" name="debug_level"/>
        <parameter valueString="true" name="muldiv_divider"/>
        <parameter valueString="false" name="dcache_bursts"/>
        <parameter valueString="true" name="setting_activateMonitors"/>
        <parameter valueString="true" name="setting_bit31BypassDCache"/>
        <parameter valueString="Automatic" name="icache_ramBlockType"/>
        <parameter valueString="_8" name="setting_bhtPtrSz"/>
        <parameter valueString="false" name="setting_preciseDivisionErrorException"/>
        <parameter valueString="false" name="setting_preciseSlaveAccessErrorException"/>
        <parameter valueString="false" name="debug_debugReqSignals"/>
        <parameter valueString="_6" name="mmu_udtlbNumEntries"/>
        <parameter valueString="_1" name="dcache_numTCDM"/>
        <parameter valueString="false" name="setting_fullWaveformSignals"/>
        <parameter valueString="false" name="setting_performanceCounter"/>
        <parameter valueString="_7" name="mmu_itlbPtrSz"/>
        <parameter valueString="_4096" name="dcache_size"/>
        <parameter valueString="Automatic" name="dcache_ramBlockType"/>
        <parameter valueString="true" name="setting_activateTrace"/>
        <parameter valueString="false" name="setting_HBreakTest"/>
        <parameter valueString="false" name="setting_exportPCB"/>
        <parameter valueString="false" name="setting_activateTestEndChecker"/>
        <parameter valueString="None" name="icache_burstType"/>
        <parameter valueString="false" name="setting_showUnpublishedSettings"/>
        <parameter valueString="true" name="debug_triggerArming"/>
        <parameter valueString="false" name="mmu_enabled"/>
    </module>
    <module version="7.2" name="flash_ssram_tristate_bridge" kind="altera_avalon_tri_state_bridge">
        <parameter valueString="true" name="registerIncomingSignals"/>
    </module>
    <module version="7.2" name="ext_ssram" kind="altera_avalon_cy7c1380_ssram">
        <parameter valueString="s1/address,s1/data" name="sharedPorts"/>
        <parameter valueString="2" name="readLatency"/>
        <parameter valueString="true" name="simMakeModel"/>
        <parameter valueString="1" name="size"/>
    </module>
    <module version="7.2" name="ext_flash" kind="altera_avalon_cfi_flash">
        <parameter valueString="16" name="dataWidth"/>
        <parameter valueString="s1/address,s1/data" name="sharedPorts"/>
        <parameter valueString="20" name="holdTime"/>
        <parameter valueString="30.0" name="actualSetupTime"/>
        <parameter valueString="70.0" name="actualWaitTime"/>
        <parameter valueString="20.0" name="actualHoldTime"/>
        <parameter valueString="INTEL128P30" name="corePreset"/>
        <parameter valueString="NS" name="timingUnits"/>
        <parameter valueString="70" name="waitTime"/>
        <parameter valueString="25" name="setupTime"/>
        <parameter valueString="23" name="addressWidth"/>
    </module>
    <module version="7.2" name="altmemddr" kind="altmemddr">
        <parameter valueString="200.0" name="mem_if_tinit_us"/>
        <parameter valueString="Cyclone III" name="family"/>
        <parameter name="mem_asrm">Manual SR Reference (SRT)</parameter>
        <parameter valueString="8" name="mem_if_dq_per_dqs"/>
        <parameter valueString="400" name="mem_tdqsq_ps"/>
        <parameter valueString="533.0" name="mem_tcl_60_fmax"/>
        <parameter valueString="4" name="WIDTH_RATIO"/>
        <parameter valueString="(9091 ps)" name="mem_if_clk_ps_label"/>
        <parameter valueString="false" name="mem_if_oct_en"/>
        <parameter valueString="9" name="mem_if_coladdr_width"/>
        <parameter valueString="Dynamic ODT off" name="mem_rtt_wr"/>
        <parameter valueString="false" name="dll_external"/>
        <parameter valueString="false" name="pll_reconfig_ports_en"/>
        <parameter valueString="200.0" name="mem_fmax"/>
        <parameter valueString="15.0" name="mem_if_trcd_ns"/>
        <parameter valueString="5.0" name="mem_wtcl"/>
        <parameter valueString="50.0" name="pll_ref_clk_mhz"/>
        <parameter valueString="40.0" name="mem_if_tras_ns"/>
        <parameter valueString="10.0" name="mem_if_tmrd_ns"/>
        <parameter valueString="1" name="mem_if_cs_per_dimm"/>
        <parameter valueString="2" name="mem_bl"/>
        <parameter valueString="false" name="mem_if_dqsn_en"/>
        <parameter valueString="Normal" name="mem_srtr"/>
        <parameter valueString="Normal" name="mem_drv_str"/>
        <parameter valueString="0.2" name="mem_tdss_ck"/>
        <parameter valueString="false" name="user_refresh_en"/>
        <parameter valueString="PSC A2S56D40CTP-G5" name="mem_if_preset"/>
        <parameter valueString="true" name="local_if_type_avalon"/>
        <parameter valueString="8" name="speed_grade"/>
        <parameter valueString="533.0" name="mem_tcl_40_fmax"/>
        <parameter valueString="DDR SDRAM" name="mem_if_memtype"/>
        <parameter valueString="1" name="mem_if_clk_pair_count"/>
        <parameter valueString="Other" name="vendor"/>
        <parameter valueString="70.0" name="mem_if_trfc_ns"/>
        <parameter valueString="400.0" name="mem_tcl_80_fmax"/>
        <parameter valueString="Sequential" name="mem_btype"/>
        <parameter valueString="133.333" name="mem_tcl_20_fmax"/>
        <parameter valueString="0.28" name="mem_tdqss_ck"/>
        <parameter valueString="Predefined Pattern" name="mem_mpr_oper"/>
        <parameter valueString="false" name="ctl_ecc_en"/>
        <parameter valueString="Yes" name="mem_dll_en"/>
        <parameter valueString="1" name="mem_if_cs_width"/>
        <parameter valueString="15.0" name="mem_if_twr_ns"/>
        <parameter valueString="400" name="mem_tdha_ps"/>
        <parameter valueString="20" name="board_skew_ps"/>
        <parameter valueString="90" name="ac_phase"/>
        <parameter valueString="600" name="mem_tisa_ps"/>
        <parameter valueString="(110.0 MHz)" name="local_if_clk_mhz_label"/>
        <parameter valueString="0" name="input_period"/>
        <parameter valueString="7.0" name="mem_if_trefi_us"/>
        <parameter valueString="false" name="debug_en"/>
        <parameter valueString="Full Array" name="mem_pasr"/>
        <parameter valueString="true" name="fast_simulation_en"/>
        <parameter valueString="Disabled" name="mem_atcl"/>
        <parameter valueString="533.0" name="mem_tcl_50_fmax"/>
        <parameter valueString="Discrete Device" name="chip_or_dimm"/>
        <parameter valueString="Full" name="local_if_drate"/>
        <parameter valueString="SOPC_BUILDER" name="tool_context"/>
        <parameter valueString="Disabled" name="mem_odt"/>
        <parameter valueString="10" name="mem_if_pchaddr_bit"/>
        <parameter valueString="0.2" name="mem_tdsh_ck"/>
        <parameter valueString="(20000 ps)" name="pll_ref_clk_ps_label"/>
        <parameter valueString="200.0" name="mem_tcl_25_fmax"/>
        <parameter valueString="2" name="mem_if_bankaddr_width"/>
        <parameter valueString="400.0" name="mem_tcl_90_fmax"/>
        <parameter name="dedicated_memory_clk_phase_label">Dedicated memory clock phase:</parameter>
        <parameter valueString="400" name="mem_tdsa_ps"/>
        <parameter valueString="false" name="mem_dyn_deskew_en"/>
        <parameter valueString="Cyclone III" name="project_family"/>
        <parameter valueString="32" name="local_if_dwidth_label"/>
        <parameter valueString="Yes" name="mem_if_dm_pins_en"/>
        <parameter valueString="400.0" name="mem_tcl_100_fmax"/>
        <parameter valueString="550" name="mem_tdqsck_ps"/>
        <parameter valueString="16" name="mem_if_dwidth"/>
        <parameter valueString="false" name="dedicated_memory_clk_en"/>
        <parameter valueString="Predefined Pattern" name="mem_mpr_loc"/>
        <parameter valueString="533.0" name="mem_tcl_15_fmax"/>
        <parameter valueString="0" name="dedicated_memory_clk_phase"/>
        <parameter valueString="Fast Exit" name="mem_dll_pch"/>
        <parameter valueString="500" name="mem_tqhs_ps"/>
        <parameter valueString="700" name="mem_tac_ps"/>
        <parameter valueString="1" name="avalon_burst_length"/>
        <parameter valueString="2" name="mem_if_twtr_ck"/>
        <parameter valueString="true" name="use_generated_memory_model"/>
        <parameter valueString="600" name="mem_tiha_ps"/>
        <parameter valueString="200.0" name="mem_tcl_30_fmax"/>
        <parameter valueString="400.0" name="mem_tcl_70_fmax"/>
        <parameter valueString="90" name="ac_clk_select"/>
        <parameter valueString="ODT Disabled" name="mem_rtt_nom"/>
        <parameter valueString="110.0" name="mem_if_clk_mhz"/>
        <parameter valueString="3.0" name="mem_tcl"/>
        <parameter valueString="15.0" name="mem_if_trp_ns"/>
        <parameter valueString="RZQ/7" name="mem_drv_impedance"/>
        <parameter valueString="13" name="mem_if_rowaddr_width"/>
    </module>
    <module version="7.2" name="altmemddr_bridge" kind="altera_avalon_clock_crossing">
        <parameter valueString="32" name="dataWidth"/>
        <parameter valueString="8" name="downstreamFIFODepth"/>
        <parameter valueString="23" name="slaveAddressWidth"/>
        <parameter valueString="64" name="upstreamFIFODepth"/>
        <parameter valueString="false" name="upstreamUseRegister"/>
        <parameter valueString="8" name="maxBurstSize"/>
        <parameter valueString="false" name="downstreamUseRegister"/>
        <parameter valueString="false" name="useBurstCount"/>
    </module>
    <module version="7.2" name="pipeline_bridge_peripherals" kind="altera_avalon_pipeline_bridge">
        <parameter valueString="32" name="dataWidth"/>
        <parameter valueString="true" name="waitrequestPipeline"/>
        <parameter valueString="true" name="upstreamPipeline"/>
        <parameter valueString="6" name="slaveAddressWidth"/>
        <parameter valueString="2" name="maxBurstSize"/>
        <parameter valueString="false" name="enableArbiterlock"/>
        <parameter valueString="3" name="maximumPendingReadTransactions"/>
        <parameter valueString="false" name="burstEnable"/>
        <parameter valueString="true" name="downstreamPipeline"/>
    </module>
    <module version="7.2" name="jtag_uart" kind="altera_avalon_jtag_uart">
        <parameter valueString="8" name="readIRQThreshold"/>
        <parameter valueString="" name="simInputCharacterStream"/>
        <parameter valueString="0" name="hubInstanceID"/>
        <parameter valueString="64" name="readBufferDepth"/>
        <parameter valueString="false" name="allowMultipleConnections"/>
        <parameter valueString="64" name="writeBufferDepth"/>
        <parameter valueString="8" name="writeIRQThreshold"/>
        <parameter valueString="false" name="useRegistersForWriteBuffer"/>
        <parameter valueString="false" name="useRegistersForReadBuffer"/>
        <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
    </module>
    <module version="7.2" name="button_pio" kind="altera_avalon_pio">
        <parameter valueString="RISING" name="edgeType"/>
        <parameter valueString="4" name="width"/>
        <parameter valueString="Input" name="direction"/>
        <parameter valueString="EDGE" name="irqType"/>
        <parameter valueString="true" name="captureEdge"/>
        <parameter valueString="true" name="simDoTestBenchWiring"/>
        <parameter valueString="true" name="generateIRQ"/>
        <parameter valueString="false" name="bitClearingEdgeCapReg"/>
        <parameter valueString="15" name="simDrivenValue"/>
    </module>
    <module version="7.2" name="sys_clk_timer" kind="altera_avalon_timer">
        <parameter valueString="FULL_FEATURED" name="timerPreset"/>
        <parameter valueString="10.0" name="period"/>
        <parameter valueString="false" name="resetOutput"/>
        <parameter valueString="MSEC" name="periodUnits"/>
        <parameter valueString="false" name="fixedPeriod"/>
        <parameter valueString="false" name="alwaysRun"/>
        <parameter valueString="false" name="timeoutPulseOutput"/>
        <parameter valueString="true" name="snapshot"/>
    </module>
    <module version="7.2" name="high_res_timer" kind="altera_avalon_timer">
        <parameter valueString="FULL_FEATURED" name="timerPreset"/>
        <parameter valueString="10.0" name="period"/>
        <parameter valueString="false" name="resetOutput"/>
        <parameter valueString="USEC" name="periodUnits"/>
        <parameter valueString="false" name="fixedPeriod"/>
        <parameter valueString="false" name="alwaysRun"/>
        <parameter valueString="false" name="timeoutPulseOutput"/>
        <parameter valueString="true" name="snapshot"/>
    </module>
    <module version="7.2" name="onchip_ram" kind="altera_avalon_onchip_memory2">
        <parameter valueString="32" name="dataWidth"/>
        <parameter valueString="true" name="dualPort"/>
        <parameter valueString="true" name="writable"/>
        <parameter valueString="1" name="slave1Latency"/>
        <parameter valueString="true" name="initMemContent"/>
        <parameter valueString="onchip_ram" name="initializationFileName"/>
        <parameter valueString="false" name="useNonDefaultInitFile"/>
        <parameter valueString="false" name="allowInSystemMemoryContentEditor"/>
        <parameter valueString="1" name="slave2Latency"/>
        <parameter valueString="false" name="simAllowMRAMContentsFile"/>
        <parameter valueString="false" name="useShallowMemBlocks"/>
        <parameter valueString="AUTO" name="blockType"/>
        <parameter valueString="NONE" name="instanceID"/>
        <parameter valueString="32768" name="memorySize"/>
    </module>
    <module version="7.2" name="led_pio" kind="altera_avalon_pio">
        <parameter valueString="RISING" name="edgeType"/>
        <parameter valueString="2" name="width"/>
        <parameter valueString="Output" name="direction"/>
        <parameter valueString="LEVEL" name="irqType"/>
        <parameter valueString="false" name="captureEdge"/>
        <parameter valueString="false" name="simDoTestBenchWiring"/>
        <parameter valueString="false" name="generateIRQ"/>
        <parameter valueString="false" name="bitClearingEdgeCapReg"/>
        <parameter valueString="0" name="simDrivenValue"/>
    </module>
    <module version="7.2" name="sysid" kind="altera_avalon_sysid">
        <parameter valueString="1205699706" name="timestamp"/>
        <parameter valueString="477920688" name="id"/>
    </module>
    <module version="7.2" name="sys_pll" kind="altera_avalon_pll">
        <parameter name="e2">tap e2 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0 
</parameter>
        <parameter name="c0">tap c0 mult 2 div 1 phase 0 enabled true inputfreq 50000000 outputfreq 100000000 
</parameter>
        <parameter name="c7">tap c7 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0 
</parameter>
        <parameter valueString="Register" name="resetInputPortOption"/>
        <parameter valueString="CYCLONEIII" name="deviceFamily"/>
        <parameter valueString="50000000" name="inputClockFrequency"/>
        <parameter valueString="Export" name="lockedOutputPortOption"/>
        <parameter name="e3">tap e3 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0 
</parameter>
        <parameter name="c1">tap c1 mult 2 div 1 phase -2000 enabled true inputfreq 50000000 outputfreq 100000000 
</parameter>
        <parameter name="c6">tap c6 mult 1 div 1 phase 0 enabled false inputfreq 0 outputfreq 0 
</parameter>
        <parameter name="pllHdl">//  megafunction wizard: %ALTPLL%