cycloneiii_3c25_start_niosii_standard.sdc

nios里面用自定义指令集来实现三角函数

### Creating and setting variables for clock paths to make code look cleaner
set System_Clock_int *|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]
set SSRAM_Clock_ext *|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]
set DDR_SOPC_Clock *|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_ciii_inst|clk|pll|altpll_component|auto_generated|pll1|clk[1]

create_clock -period 100 -name {altera_reserved_tck} [get_ports {altera_reserved_tck}]

set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks $DDR_SOPC_Clock]
set_false_path -from [get_clocks $DDR_SOPC_Clock] -to [get_clocks $System_Clock_int]

set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $System_Clock_int]
set_false_path -from [get_clocks $System_Clock_int] -to [get_clocks {osc_clk}]

set_false_path -from [get_clocks {osc_clk}] -to [get_clocks $DDR_SOPC_Clock]
set_false_path -from [get_clocks $DDR_SOPC_Clock] -to [get_clocks {osc_clk}]

##SSRAM Constraints
set_output_delay -clock [get_clocks $SSRAM_Clock_ext] -reference_pin [get_ports {ssram_clk}] 2.4 [get_ports {ssram_adsc_n ssram_bw_n* ssram_bwe_n ssram_ce_n ssram_oe_n flash_ssram_a* flash_ssram_d*}]
set_input_delay -clock [get_clocks $SSRAM_Clock_ext]  -reference_pin [get_ports {ssram_clk}] 4.1 [get_ports {flash_ssram_d*}]
set_multicycle_path -from [get_ports {flash_ssram_d*} ] -setup -end 2