altmemddr_phy_report_timing.tcl

来自「nios里面用自定义指令集来实现三角函数」· TCL 代码 · 共 407 行 · 第 1/2 页

##
##Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
##use of Altera Corporation's design tools, logic functions and other
##software and tools, and its AMPP partner logic functions, and any
##output files any of the foregoing (including device programming or
##simulation files), and any associated documentation or information are
##expressly subject to the terms and conditions of the Altera Program
##License Subscription Agreement or other applicable license agreement,
##including, without limitation, that your use is for the sole purpose
##of programming logic devices manufactured by Altera and sold by Altera
##or its authorized distributors. Please refer to the applicable
##agreement for further details.
if { ![info exists quartus(nameofexecutable)] || $quartus(nameofexecutable) != "quartus_sta" } {
	puts "Restarting in quartus_sta..."
   set cmd quartus_sta
   if { [info exists quartus(binpath)] } {
     set cmd [file join $quartus(binpath) $cmd]
   }
	set res [catch { exec $cmd -t [info script] batch } output]
	# This procedure is 'clever' in that it will write a message using
	# post_message if available and refert to puts otherwise.
	# if post_message fails, this procedure changes itself into one that
	# uses a simple 'puts' and continues.
	proc out { msg } {
     set type info
     regexp {^\W*(Info|Extra Info|Warning|Critical Warning|Error): (.*)$} $msg x type msg
     regsub " " $type _ type
    if { [catch { post_message -type $type $msg } res] } {
    	proc out { msg } {puts $msg}
    	out $msg
    }
	}
	foreach line [split $output \n] {
    out $line
	}
	return 0
}

set scriptname [info script]
if { ! [regexp (.*)_report_timing.tcl $scriptname _ corename] } {
	error "Couldn't determine corename from $scriptname"
}


if {[namespace which -variable ::argv] != "" && [lindex $::argv 0] == "batch" } {
  post_message -type info "Running in batch mode"
  set proj_name [glob *.qpf]
  project_open -revision [get_current_revision $proj_name] $proj_name
  catch {delete_timing_netlist }
  create_timing_netlist
  read_sdc
  set opcs [list]
  foreach_in_collection op [get_available_operating_conditions] {
    lappend opcs $op
  }
	update_timing_netlist
} else {
  set opcs [list ""]
} 
set dirname [file dirname [info script]] 
set fn [file join $dirname ${corename}_cu.tcl]
if { $::TimeQuestInfo(family) == "HardCopy II" &&  [file exists $fn]} {
  source [file join $dirname $fn]
  foreach s [list fpga_tREAD_CAPTURE_SETUP_ERROR fpga_tREAD_CAPTURE_HOLD_ERROR fpga_RESYNC_SETUP_ERROR fpga_RESYNC_HOLD_ERROR fpga_PA_DQS_SETUP_ERROR fpga_PA_DQS_HOLD_ERROR WR_DQS_DQ_SETUP_ERROR WR_DQS_DQ_HOLD_ERROR fpga_tCK_ADDR_CTRL_SETUP_ERROR fpga_tCK_ADDR_CTRL_HOLD_ERROR fpga_tDQSS_SETUP_ERROR fpga_tDQSS_HOLD_ERROR fpga_tDSSH_SETUP_ERROR fpga_tDSSH_HOLD_ERROR] {
    if { ! [info exists $s] } {
      post_message -type critical_warning "ALTMEMPHY: Missing setting in $fn:$s"
    }
  }
} else {
  if { $::TimeQuestInfo(family) == "HardCopy II" } {
    if { $::TimeQuestInfo(nameofexecutable) != "quartus_fit"} {
      post_message -type warning "HardCopy II clock uncertainty file $fn could not be found"
    }
  }
set fpga_tREAD_CAPTURE_SETUP_ERROR 0
set fpga_tREAD_CAPTURE_HOLD_ERROR 0
set fpga_RESYNC_SETUP_ERROR 0
set fpga_RESYNC_HOLD_ERROR 0
set fpga_PA_DQS_SETUP_ERROR 0
set fpga_PA_DQS_HOLD_ERROR 0
set WR_DQS_DQ_SETUP_ERROR 0
set WR_DQS_DQ_HOLD_ERROR 0
set fpga_tCK_ADDR_CTRL_SETUP_ERROR 0
set fpga_tCK_ADDR_CTRL_HOLD_ERROR 0
set fpga_tDQSS_SETUP_ERROR 0
set fpga_tDQSS_HOLD_ERROR 0
set fpga_tDSSH_SETUP_ERROR 0
set fpga_tDSSH_HOLD_ERROR 0
}
set period 9.090
load_package atoms
read_atom_netlist
proc traverse_atom_path {atom_id atom_oport_id path} {
  # Return list of {atom oterm_id} pairs by tracing the atom netlist starting from the given atom_id through the given path
  # Path consists of list of {atom_type fanin|fanout|end <port_type> <-optional>}
  set result [list]
  if {[llength $path] > 0} {
    set path_point [lindex $path 0]
    set atom_type [lindex $path_point 0]
    set next_direction [lindex $path_point 1]
    set port_type [lindex $path_point 2]
    set atom_optional [lindex $path_point 3]
    if {[get_atom_node_info -key type -node $atom_id] == $atom_type} {
      if {$next_direction == "end"} {
        if {[get_atom_port_info -key type -node $atom_id -port_id $atom_oport_id -type oport] == $port_type} {
          lappend result [list $atom_id $atom_oport_id]
        }
      } elseif {$next_direction == "fanin"} {
        set atom_iport [get_atom_iport_by_type -node $atom_id -type $port_type]
        if {$atom_iport != -1} {
          set iport_fanin [get_atom_port_info -key fanin -node $atom_id -port_id $atom_iport -type iport]
          set source_atom [lindex $iport_fanin 0]
          set source_oterm [lindex $iport_fanin 1]
          set result [traverse_atom_path $source_atom $source_oterm [lrange $path 1 end]]
        }
      } elseif {$next_direction == "fanout"} {
        set atom_oport [get_atom_oport_by_type -node $atom_id -type $port_type]
        if {$atom_oport != -1} {
          set oport_fanout [get_atom_port_info -key fanout -node $atom_id -port_id $atom_oport -type oport]
          foreach dest $oport_fanout {
            set dest_atom [lindex $dest 0]
            set dest_iterm [lindex $dest 1]
            set fanout_result_list [traverse_atom_path $dest_atom -1 [lrange $path 1 end]]
            foreach fanout_result $fanout_result_list {
              if {[lsearch $result $fanout_result] == -1} {
                lappend result $fanout_result
              }
            }
          }
        }
      } else {
        error "Unexpected path"
      }
    } elseif {$atom_optional == "-optional"} {
    	set result [traverse_atom_path $atom_id $atom_oport_id [lrange $path 1 end]]
    }
  }
  return $result
}


# Get the fitter name of the PLL output driving the given pin
proc traverse_to_ddio_out_pll_clock {pin msg_list_name} {
  upvar 1 $msg_list_name msg_list
  set result ""
  if {$pin != ""} {
    set pin_id [get_atom_node_by_name -name $pin]
    set pin_to_pll_path [list {IO_PAD fanin PADIN} {IO_OBUF fanin I} {PSEUDO_DIFF_OUT fanin I -optional} {DDIO_OUT fanin CLKHI -optional} {CLKBUF fanin INCLK -optional} {PLL end CLK}]
    set pll_id_list [traverse_atom_path $pin_id -1 $pin_to_pll_path]
    if {[llength $pll_id_list] == 1} {
      set atom_oterm_pair [lindex $pll_id_list 0]
      set result [get_atom_port_info -key name -node [lindex $atom_oterm_pair 0] -port_id [lindex $atom_oterm_pair 1] -type oport]
    } else {
      lappend msg_list "Error: PLL clock not found for $pin"
    }
  }
  return $result
}

proc verify_high_performance_timing_assumptions {instname pin_array_name} {
  upvar 1 $pin_array_name pins
  set num_errors 0
  load_package verify_ddr
  set ck_pins [lsort $pins(ck_p)]
  set ckn_pins [lsort $pins(ck_n)]
  set ck_ckn_pairs [list]
  set failed_assumptions [list]
  if {[llength $ck_pins] > 0 && [llength $ck_pins] == [llength $ckn_pins]} {
  	for {set ck_index 0} {$ck_index != [llength $ck_pins]} {incr ck_index} {
    	lappend ck_ckn_pairs [list [lindex $ck_pins $ck_index] [lindex $ckn_pins $ck_index]]
    }
  } else {
    incr num_errors
    lappend failed_assumptions "Error: Could not locate same number of CK pins as CK# pins"
  }
  set read_pins_list [list]
  set write_pins_list [list]
  foreach dqsgroup $pins(dqsgroup) {
    set dqs [lindex $dqsgroup 0]
    set dq_list [lindex $dqsgroup 2]
    lappend read_pins_list [list $dqs $dq_list]
    set dm_list [lindex $dqsgroup 1]
    lappend write_pins_list [list $dqs [concat $dq_list $dm_list]]
  }
  set all_write_dqs_list [get_all_dqs_pins $pins(dqsgroup)]
  set all_d_list [get_all_dq_pins $pins(dqsgroup)]
  if {[llength $pins(dqsgroup)] == 0} {
    incr num_errors
    lappend failed_assumptions "Error: Could not locate DQS pins"
  }

  if {$num_errors == 0} {
    set msg_list [list]
    set clk_to_write_d [traverse_to_ddio_out_pll_clock [lindex $all_d_list 0] msg_list]
    set clk_to_write_clock [traverse_to_ddio_out_pll_clock [lindex $all_write_dqs_list 0] msg_list]
    set clk_to_ck_ckn [traverse_to_ddio_out_pll_clock [lindex $ck_pins 0] msg_list]
    foreach msg $msg_list {
      set verify_assumptions_exception 1
      incr num_errors
      lappend failed_assumptions $msg
    }
    if {$num_errors == 0} {
      #puts "calling verify_assumptions -memory_type ddr -read_pins_list $read_pins_list -write_pins_list $write_pins_list -ck_ckn_pairs $ck_ckn_pairs -clk_to_write_d $clk_to_write_d -clk_to_write_clock $clk_to_write_clock -clk_to_ck_ckn $clk_to_ck_ckn -mimic_pin [lindex $ck_pins 0]  "
      set verify_assumptions_exception 0