📄 cycloneiii_3c25_start_niosii_standard_sopc.v
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assign altmemddr_s1_resetrequest_n_from_sa = altmemddr_s1_resetrequest_n;
//altmemddr_s1_firsttransfer first transaction, which is an e_assign
assign altmemddr_s1_firsttransfer = altmemddr_s1_begins_xfer ? altmemddr_s1_unreg_firsttransfer : altmemddr_s1_reg_firsttransfer;
//altmemddr_s1_unreg_firsttransfer first transaction, which is an e_assign
assign altmemddr_s1_unreg_firsttransfer = ~(altmemddr_s1_slavearbiterlockenable & altmemddr_s1_any_continuerequest);
//altmemddr_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
altmemddr_s1_reg_firsttransfer <= 1'b1;
else if (altmemddr_s1_begins_xfer)
altmemddr_s1_reg_firsttransfer <= altmemddr_s1_unreg_firsttransfer;
end
//altmemddr_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign altmemddr_s1_beginbursttransfer_internal = altmemddr_s1_begins_xfer;
//altmemddr/s1 begin burst transfer to slave, which is an e_assign
assign altmemddr_s1_beginbursttransfer = altmemddr_s1_beginbursttransfer_internal;
//altmemddr_s1_read assignment, which is an e_mux
assign altmemddr_s1_read = altmemddr_bridge_m1_granted_altmemddr_s1 & altmemddr_bridge_m1_read;
//altmemddr_s1_write assignment, which is an e_mux
assign altmemddr_s1_write = altmemddr_bridge_m1_granted_altmemddr_s1 & altmemddr_bridge_m1_write;
assign shifted_address_to_altmemddr_s1_from_altmemddr_bridge_m1 = altmemddr_bridge_m1_address_to_slave;
//altmemddr_s1_address mux, which is an e_mux
assign altmemddr_s1_address = shifted_address_to_altmemddr_s1_from_altmemddr_bridge_m1 >> 2;
//d1_altmemddr_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_altmemddr_s1_end_xfer <= 1;
else if (1)
d1_altmemddr_s1_end_xfer <= altmemddr_s1_end_xfer;
end
//altmemddr_s1_waits_for_read in a cycle, which is an e_mux
assign altmemddr_s1_waits_for_read = altmemddr_s1_in_a_read_cycle & ~altmemddr_s1_waitrequest_n_from_sa;
//altmemddr_s1_in_a_read_cycle assignment, which is an e_assign
assign altmemddr_s1_in_a_read_cycle = altmemddr_bridge_m1_granted_altmemddr_s1 & altmemddr_bridge_m1_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = altmemddr_s1_in_a_read_cycle;
//altmemddr_s1_waits_for_write in a cycle, which is an e_mux
assign altmemddr_s1_waits_for_write = altmemddr_s1_in_a_write_cycle & ~altmemddr_s1_waitrequest_n_from_sa;
//altmemddr_s1_in_a_write_cycle assignment, which is an e_assign
assign altmemddr_s1_in_a_write_cycle = altmemddr_bridge_m1_granted_altmemddr_s1 & altmemddr_bridge_m1_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = altmemddr_s1_in_a_write_cycle;
assign wait_for_altmemddr_s1_counter = 0;
//altmemddr_s1_byteenable byte enable port mux, which is an e_mux
assign altmemddr_s1_byteenable = (altmemddr_bridge_m1_granted_altmemddr_s1)? altmemddr_bridge_m1_byteenable :
-1;
//burstcount mux, which is an e_mux
assign altmemddr_s1_burstcount = 1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//altmemddr/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else if (1)
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cycloneIII_3c25_start_niosII_standard_sopc_reset_osc_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else if (1)
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (1)
data_out <= data_in_d1;
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_data_master_to_altmemddr_bridge_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_10;
reg full_11;
reg full_12;
reg full_13;
reg full_14;
reg full_15;
reg full_16;
reg full_17;
reg full_18;
reg full_19;
reg full_2;
reg full_20;
reg full_21;
reg full_22;
reg full_23;
reg full_24;
reg full_25;
reg full_26;
reg full_27;
reg full_28;
reg full_29;
reg full_3;
reg full_30;
reg full_31;
reg full_32;
reg full_33;
reg full_34;
reg full_35;
reg full_36;
reg full_37;
reg full_38;
reg full_39;
reg full_4;
reg full_40;
reg full_41;
reg full_42;
reg full_43;
reg full_44;
reg full_45;
reg full_46;
reg full_47;
wire full_48;
reg full_5;
reg full_6;
reg full_7;
reg full_8;
reg full_9;
reg [ 6: 0] how_many_ones;
wire [ 6: 0] one_count_minus_one;
wire [ 6: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p10_full_10;
wire p10_stage_10;
wire p11_full_11;
wire p11_stage_11;
wire p12_full_12;
wire p12_stage_12;
wire p13_full_13;
wire p13_stage_13;
wire p14_full_14;
wire p14_stage_14;
wire p15_full_15;
wire p15_stage_15;
wire p16_full_16;
wire p16_stage_16;
wire p17_full_17;
wire p17_stage_17;
wire p18_full_18;
wire p18_stage_18;
wire p19_full_19;
wire p19_stage_19;
wire p1_full_1;
wire p1_stage_1;
wire p20_full_20;
wire p20_stage_20;
wire p21_full_21;
wire p21_stage_21;
wire p22_full_22;
wire p22_stage_22;
wire p23_full_23;
wire p23_stage_23;
wire p24_full_24;
wire p24_stage_24;
wire p25_full_25;
wire p25_stage_25;
wire p26_full_26;
wire p26_stage_26;
wire p27_full_27;
wire p27_stage_27;
wire p28_full_28;
wire p28_stage_28;
wire p29_full_29;
wire p29_stage_29;
wire p2_full_2;
wire p2_stage_2;
wire p30_full_30;
wire p30_stage_30;
wire p31_full_31;
wire p31_stage_31;
wire p32_full_32;
wire p32_stage_32;
wire p33_full_33;
wire p33_stage_33;
wire p34_full_34;
wire p34_stage_34;
wire p35_full_35;
wire p35_stage_35;
wire p36_full_36;
wire p36_stage_36;
wire p37_full_37;
wire p37_stage_37;
wire p38_full_38;
wire p38_stage_38;
wire p39_full_39;
wire p39_stage_39;
wire p3_full_3;
wire p3_stage_3;
wire p40_full_40;
wire p40_stage_40;
wire p41_full_41;
wire p41_stage_41;
wire p42_full_42;
wire p42_stage_42;
wire p43_full_43;
wire p43_stage_43;
wire p44_full_44;
wire p44_stage_44;
wire p45_full_45;
wire p45_stage_45;
wire p46_full_46;
wire p46_stage_46;
wire p47_full_47;
wire p47_stage_47;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
wire p7_full_7;
wire p7_stage_7;
wire p8_full_8;
wire p8_stage_8;
wire p9_full_9;
wire p9_stage_9;
reg stage_0;
reg stage_1;
reg stage_10;
reg stage_11;
reg stage_12;
reg stage_13;
reg stage_14;
reg stage_15;
reg stage_16;
reg stage_17;
reg stage_18;
reg stage_19;
reg stage_2;
reg stage_20;
reg stage_21;
reg stage_22;
reg stage_23;
reg stage_24;
reg stage_25;
reg stage_26;
reg stage_27;
reg stage_28;
reg stage_29;
reg stage_3;
reg stage_30;
reg stage_31;
reg stage_32;
reg stage_33;
reg stage_34;
reg stage_35;
reg stage_36;
reg stage_37;
reg stage_38;
reg stage_39;
reg stage_4;
reg stage_40;
reg stage_41;
reg stage_42;
reg stage_43;
reg stage_44;
reg stage_45;
reg stage_46;
reg stage_47;
reg stage_5;
reg stage_6;
reg stage_7;
reg stage_8;
reg stage_9;
wire [ 6: 0] updated_one_count;
assign data_out = stage_0;
assign full = full_47;
assign empty = !full_0;
assign full_48 = 0;
//data_47, which is an e_mux
assign p47_stage_47 = ((full_48 & ~clear_fifo) == 0)? data_in :
data_in;
//data_reg_47, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_47 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_47))
if (sync_reset & full_47 & !((full_48 == 0) & read & write))
stage_47 <= 0;
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