cycloneiii_3c25_start_niosii_standard_sopc.v

nios里面用自定义指令集来实现三角函数

          full_3 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_3 <= 0;
          else 
            full_3 <= p3_full_3;
    end


  //data_2, which is an e_mux
  assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
    stage_3;

  //data_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_2 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_2))
          if (sync_reset & full_2 & !((full_3 == 0) & read & write))
              stage_2 <= 0;
          else 
            stage_2 <= p2_stage_2;
    end


  //control_2, which is an e_mux
  assign p2_full_2 = ((read & !write) == 0)? full_1 :
    full_3;

  //control_reg_2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_2 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_2 <= 0;
          else 
            full_2 <= p2_full_2;
    end


  //data_1, which is an e_mux
  assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
    stage_2;

  //data_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_1 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_1))
          if (sync_reset & full_1 & !((full_2 == 0) & read & write))
              stage_1 <= 0;
          else 
            stage_1 <= p1_stage_1;
    end


  //control_1, which is an e_mux
  assign p1_full_1 = ((read & !write) == 0)? full_0 :
    full_2;

  //control_reg_1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_1 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo)
              full_1 <= 0;
          else 
            full_1 <= p1_full_1;
    end


  //data_0, which is an e_mux
  assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
    stage_1;

  //data_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          stage_0 <= 0;
      else if (clear_fifo | sync_reset | read | (write & !full_0))
          if (sync_reset & full_0 & !((full_1 == 0) & read & write))
              stage_0 <= 0;
          else 
            stage_0 <= p0_stage_0;
    end


  //control_0, which is an e_mux
  assign p0_full_0 = ((read & !write) == 0)? 1 :
    full_1;

  //control_reg_0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          full_0 <= 0;
      else if (clear_fifo | (read ^ write) | (write & !full_0))
          if (clear_fifo & ~write)
              full_0 <= 0;
          else 
            full_0 <= p0_full_0;
    end


  assign one_count_plus_one = how_many_ones + 1;
  assign one_count_minus_one = how_many_ones - 1;
  //updated_one_count, which is an e_mux
  assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
    ((((clear_fifo | sync_reset) & write)))? |data_in :
    ((read & (|data_in) & write & (|stage_0)))? how_many_ones :
    ((write & (|data_in)))? one_count_plus_one :
    ((read & (|stage_0)))? one_count_minus_one :
    how_many_ones;

  //counts how many ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          how_many_ones <= 0;
      else if (clear_fifo | sync_reset | read | write)
          how_many_ones <= updated_one_count;
    end


  //this fifo contains ones in the data pipeline, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          fifo_contains_ones_n <= 1;
      else if (clear_fifo | sync_reset | read | write)
          fifo_contains_ones_n <= ~(|updated_one_count);
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module altmemddr_s1_arbitrator (
                                 // inputs:
                                  altmemddr_bridge_m1_address_to_slave,
                                  altmemddr_bridge_m1_byteenable,
                                  altmemddr_bridge_m1_latency_counter,
                                  altmemddr_bridge_m1_read,
                                  altmemddr_bridge_m1_write,
                                  altmemddr_bridge_m1_writedata,
                                  altmemddr_s1_readdata,
                                  altmemddr_s1_readdatavalid,
                                  altmemddr_s1_resetrequest_n,
                                  altmemddr_s1_waitrequest_n,
                                  clk,
                                  reset_n,

                                 // outputs:
                                  altmemddr_bridge_m1_granted_altmemddr_s1,
                                  altmemddr_bridge_m1_qualified_request_altmemddr_s1,
                                  altmemddr_bridge_m1_read_data_valid_altmemddr_s1,
                                  altmemddr_bridge_m1_read_data_valid_altmemddr_s1_shift_register,
                                  altmemddr_bridge_m1_requests_altmemddr_s1,
                                  altmemddr_s1_address,
                                  altmemddr_s1_beginbursttransfer,
                                  altmemddr_s1_burstcount,
                                  altmemddr_s1_byteenable,
                                  altmemddr_s1_read,
                                  altmemddr_s1_readdata_from_sa,
                                  altmemddr_s1_resetrequest_n_from_sa,
                                  altmemddr_s1_waitrequest_n_from_sa,
                                  altmemddr_s1_write,
                                  altmemddr_s1_writedata,
                                  d1_altmemddr_s1_end_xfer
                               )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           altmemddr_bridge_m1_granted_altmemddr_s1;
  output           altmemddr_bridge_m1_qualified_request_altmemddr_s1;
  output           altmemddr_bridge_m1_read_data_valid_altmemddr_s1;
  output           altmemddr_bridge_m1_read_data_valid_altmemddr_s1_shift_register;
  output           altmemddr_bridge_m1_requests_altmemddr_s1;
  output  [ 22: 0] altmemddr_s1_address;
  output           altmemddr_s1_beginbursttransfer;
  output           altmemddr_s1_burstcount;
  output  [  3: 0] altmemddr_s1_byteenable;
  output           altmemddr_s1_read;
  output  [ 31: 0] altmemddr_s1_readdata_from_sa;
  output           altmemddr_s1_resetrequest_n_from_sa;
  output           altmemddr_s1_waitrequest_n_from_sa;
  output           altmemddr_s1_write;
  output  [ 31: 0] altmemddr_s1_writedata;
  output           d1_altmemddr_s1_end_xfer;
  input   [ 24: 0] altmemddr_bridge_m1_address_to_slave;
  input   [  3: 0] altmemddr_bridge_m1_byteenable;
  input            altmemddr_bridge_m1_latency_counter;
  input            altmemddr_bridge_m1_read;
  input            altmemddr_bridge_m1_write;
  input   [ 31: 0] altmemddr_bridge_m1_writedata;
  input   [ 31: 0] altmemddr_s1_readdata;
  input            altmemddr_s1_readdatavalid;
  input            altmemddr_s1_resetrequest_n;
  input            altmemddr_s1_waitrequest_n;
  input            clk;
  input            reset_n;

  wire             altmemddr_bridge_m1_arbiterlock;
  wire             altmemddr_bridge_m1_arbiterlock2;
  wire             altmemddr_bridge_m1_continuerequest;
  wire             altmemddr_bridge_m1_granted_altmemddr_s1;
  wire             altmemddr_bridge_m1_qualified_request_altmemddr_s1;
  wire             altmemddr_bridge_m1_rdv_fifo_empty_altmemddr_s1;
  wire             altmemddr_bridge_m1_rdv_fifo_output_from_altmemddr_s1;
  wire             altmemddr_bridge_m1_read_data_valid_altmemddr_s1;
  wire             altmemddr_bridge_m1_read_data_valid_altmemddr_s1_shift_register;
  wire             altmemddr_bridge_m1_requests_altmemddr_s1;
  wire             altmemddr_bridge_m1_saved_grant_altmemddr_s1;
  wire    [ 22: 0] altmemddr_s1_address;
  wire             altmemddr_s1_allgrants;
  wire             altmemddr_s1_allow_new_arb_cycle;
  wire             altmemddr_s1_any_bursting_master_saved_grant;
  wire             altmemddr_s1_any_continuerequest;
  wire             altmemddr_s1_arb_counter_enable;
  reg     [  3: 0] altmemddr_s1_arb_share_counter;
  wire    [  3: 0] altmemddr_s1_arb_share_counter_next_value;
  wire    [  3: 0] altmemddr_s1_arb_share_set_values;
  wire             altmemddr_s1_beginbursttransfer;
  wire             altmemddr_s1_beginbursttransfer_internal;
  wire             altmemddr_s1_begins_xfer;
  wire             altmemddr_s1_burstcount;
  wire    [  3: 0] altmemddr_s1_byteenable;
  wire             altmemddr_s1_end_xfer;
  wire             altmemddr_s1_firsttransfer;
  wire             altmemddr_s1_grant_vector;
  wire             altmemddr_s1_in_a_read_cycle;
  wire             altmemddr_s1_in_a_write_cycle;
  wire             altmemddr_s1_master_qreq_vector;
  wire             altmemddr_s1_move_on_to_next_transaction;
  wire             altmemddr_s1_non_bursting_master_requests;
  wire             altmemddr_s1_read;
  wire    [ 31: 0] altmemddr_s1_readdata_from_sa;
  wire             altmemddr_s1_readdatavalid_from_sa;
  reg              altmemddr_s1_reg_firsttransfer;
  wire             altmemddr_s1_resetrequest_n_from_sa;
  reg              altmemddr_s1_slavearbiterlockenable;
  wire             altmemddr_s1_slavearbiterlockenable2;
  wire             altmemddr_s1_unreg_firsttransfer;
  wire             altmemddr_s1_waitrequest_n_from_sa;
  wire             altmemddr_s1_waits_for_read;
  wire             altmemddr_s1_waits_for_write;
  wire             altmemddr_s1_write;
  wire    [ 31: 0] altmemddr_s1_writedata;
  reg              d1_altmemddr_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_altmemddr_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 24: 0] shifted_address_to_altmemddr_s1_from_altmemddr_bridge_m1;
  wire             wait_for_altmemddr_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~altmemddr_s1_end_xfer;
    end


  assign altmemddr_s1_begins_xfer = ~d1_reasons_to_wait & ((altmemddr_bridge_m1_qualified_request_altmemddr_s1));
  //assign altmemddr_s1_readdata_from_sa = altmemddr_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign altmemddr_s1_readdata_from_sa = altmemddr_s1_readdata;

  assign altmemddr_bridge_m1_requests_altmemddr_s1 = (1) & (altmemddr_bridge_m1_read | altmemddr_bridge_m1_write);
  //assign altmemddr_s1_waitrequest_n_from_sa = altmemddr_s1_waitrequest_n so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign altmemddr_s1_waitrequest_n_from_sa = altmemddr_s1_waitrequest_n;

  //assign altmemddr_s1_readdatavalid_from_sa = altmemddr_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign altmemddr_s1_readdatavalid_from_sa = altmemddr_s1_readdatavalid;

  //altmemddr_s1_arb_share_counter set values, which is an e_mux
  assign altmemddr_s1_arb_share_set_values = (altmemddr_bridge_m1_granted_altmemddr_s1)? 8 :
    1;

  //altmemddr_s1_non_bursting_master_requests mux, which is an e_mux
  assign altmemddr_s1_non_bursting_master_requests = altmemddr_bridge_m1_requests_altmemddr_s1;

  //altmemddr_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign altmemddr_s1_any_bursting_master_saved_grant = 0;

  //altmemddr_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign altmemddr_s1_arb_share_counter_next_value = altmemddr_s1_firsttransfer ? (altmemddr_s1_arb_share_set_values - 1) : |altmemddr_s1_arb_share_counter ? (altmemddr_s1_arb_share_counter - 1) : 0;

  //altmemddr_s1_allgrants all slave grants, which is an e_mux
  assign altmemddr_s1_allgrants = |altmemddr_s1_grant_vector;

  //altmemddr_s1_end_xfer assignment, which is an e_assign
  assign altmemddr_s1_end_xfer = ~(altmemddr_s1_waits_for_read | altmemddr_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_altmemddr_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_altmemddr_s1 = altmemddr_s1_end_xfer & (~altmemddr_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //altmemddr_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign altmemddr_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_altmemddr_s1 & altmemddr_s1_allgrants) | (end_xfer_arb_share_counter_term_altmemddr_s1 & ~altmemddr_s1_non_bursting_master_requests);

  //altmemddr_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          altmemddr_s1_arb_share_counter <= 0;
      else if (altmemddr_s1_arb_counter_enable)
          altmemddr_s1_arb_share_counter <= altmemddr_s1_arb_share_counter_next_value;
    end


  //altmemddr_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          altmemddr_s1_slavearbiterlockenable <= 0;
      else if ((|altmemddr_s1_master_qreq_vector & end_xfer_arb_share_counter_term_altmemddr_s1) | (end_xfer_arb_share_counter_term_altmemddr_s1 & ~altmemddr_s1_non_bursting_master_requests))
          altmemddr_s1_slavearbiterlockenable <= |altmemddr_s1_arb_share_counter_next_value;
    end


  //altmemddr_bridge/m1 altmemddr/s1 arbiterlock, which is an e_assign
  assign altmemddr_bridge_m1_arbiterlock = altmemddr_s1_slavearbiterlockenable & altmemddr_bridge_m1_continuerequest;

  //altmemddr_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign altmemddr_s1_slavearbiterlockenable2 = |altmemddr_s1_arb_share_counter_next_value;

  //altmemddr_bridge/m1 altmemddr/s1 arbiterlock2, which is an e_assign
  assign altmemddr_bridge_m1_arbiterlock2 = altmemddr_s1_slavearbiterlockenable2 & altmemddr_bridge_m1_continuerequest;

  //altmemddr_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign altmemddr_s1_any_continuerequest = 1;

  //altmemddr_bridge_m1_continuerequest continued request, which is an e_assign
  assign altmemddr_bridge_m1_continuerequest = 1;

  assign altmemddr_bridge_m1_qualified_request_altmemddr_s1 = altmemddr_bridge_m1_requests_altmemddr_s1 & ~((altmemddr_bridge_m1_read & ((altmemddr_bridge_m1_latency_counter != 0) | (1 < altmemddr_bridge_m1_latency_counter))));
  //unique name for altmemddr_s1_move_on_to_next_transaction, which is an e_assign
  assign altmemddr_s1_move_on_to_next_transaction = altmemddr_s1_readdatavalid_from_sa;

  //rdv_fifo_for_altmemddr_bridge_m1_to_altmemddr_s1, which is an e_fifo_with_registered_outputs
  rdv_fifo_for_altmemddr_bridge_m1_to_altmemddr_s1_module rdv_fifo_for_altmemddr_bridge_m1_to_altmemddr_s1
    (
      .clear_fifo           (1'b0),
      .clk                  (clk),
      .data_in              (altmemddr_bridge_m1_granted_altmemddr_s1),
      .data_out             (altmemddr_bridge_m1_rdv_fifo_output_from_altmemddr_s1),
      .empty                (),
      .fifo_contains_ones_n (altmemddr_bridge_m1_rdv_fifo_empty_altmemddr_s1),
      .full                 (),
      .read                 (altmemddr_s1_move_on_to_next_transaction),
      .reset_n              (reset_n),
      .sync_reset           (1'b0),
      .write                (in_a_read_cycle & ~altmemddr_s1_waits_for_read)
    );

  assign altmemddr_bridge_m1_read_data_valid_altmemddr_s1_shift_register = ~altmemddr_bridge_m1_rdv_fifo_empty_altmemddr_s1;
  //local readdatavalid altmemddr_bridge_m1_read_data_valid_altmemddr_s1, which is an e_mux
  assign altmemddr_bridge_m1_read_data_valid_altmemddr_s1 = altmemddr_s1_readdatavalid_from_sa;

  //altmemddr_s1_writedata mux, which is an e_mux
  assign altmemddr_s1_writedata = altmemddr_bridge_m1_writedata;

  //master is always granted when requested
  assign altmemddr_bridge_m1_granted_altmemddr_s1 = altmemddr_bridge_m1_qualified_request_altmemddr_s1;

  //altmemddr_bridge/m1 saved-grant altmemddr/s1, which is an e_assign
  assign altmemddr_bridge_m1_saved_grant_altmemddr_s1 = altmemddr_bridge_m1_requests_altmemddr_s1;

  //allow new arb cycle for altmemddr/s1, which is an e_assign
  assign altmemddr_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign altmemddr_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign altmemddr_s1_master_qreq_vector = 1;

  //assign altmemddr_s1_resetrequest_n_from_sa = altmemddr_s1_resetrequest_n so that symbol knows where to group signals which may go to master only, which is an e_assign