📄 altmemddr_phy.html

📁 nios里面用自定义指令集来实现三角函数
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</style></HEAD><BODY align="left" style='background-color: #ffffff;'><DIV align="left"><TABLE width="95%" border=0 cellpadding=2><TR><TD><TABLE cellpadding=2 border=0 ><TR><WIZARD></WIZARD><TD><H1>Generation Report - ALTMEMPHY v7.2</H1></TD></TR></TABLE></TD></TR><TR><TD><TABLE cellpadding=2 border=1 width="60%"><TR><TD><B>Entity Name</B></TD><TD>altmemddr_phy_alt_mem_phy_ciii</TD></TR><TR><TD><B>Variation Name</B></TD><TD>altmemddr_phy</TD></TR><TR><TD><B>Variation HDL</B></TD><TD>Verilog HDL</TD></TR><TR><TD><B>Output Directory</B></TD><TD>C:\work\rod_designs\alu_nios2_dpfp\fpu_hw_3c25_standard</TD></TR></TABLE></TD></TR><TR><TD><h2>File Summary</h2>The MegaWizard interface is creating the following files in the output directory:</TD></TR><TR><TD><TABLE cellspacing=2 cellpadding=2 border=1 width="100%"><TR align="left"><TH align="left" align="top" width="25%"><B>File</B></TH><TH align="left"><B>Description</B></TH></TR><TR><TD>altmemddr_phy.v</TD><TD>A MegaCore<small><sup>&reg</sup></small> function variation file, which defines a Verilog HDL top-level description of the custom MegaCore function.  Instantiate the entity defined by this file inside of  your design. Include this file when compiling your design in the Quartus II software.</TD></TR><TR><TD>altmemddr_phy.qip</TD><TD>Contains Quartus II project information for your MegaCore function variation.</TD></TR><TR><TD>altmemddr_phy.html</TD><TD>The MegaCore function report file.</TD></TR></TABLE></TD></TR><TR><TD><h2>MegaCore Function Variation File Ports</h2><TABLE border=1 cellpadding=2 cellspacing=0 width="75%"><TR align="left"><TH align="left"><B>Name</B></TH><TH align="left"><B>Direction</B></TH><TH align="left"><B>Width</B></TH></TR><TR><TD>pll_ref_clk</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>global_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>soft_reset_n</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>reset_request_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>phy_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>reset_phy_clk_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_address</TD><TD>INPUT</TD><TD>23</TD></TR><TR><TD>local_read_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_wdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>local_write_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_size</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_be</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>local_refresh_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_burstbegin</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>local_ready</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_rdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>local_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_init_done</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_refresh_ack</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>local_wdata_req</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_address</TD><TD>OUTPUT</TD><TD>23</TD></TR><TR><TD>ctl_read_req</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_wdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>ctl_write_req</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_size</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_be</TD><TD>OUTPUT</TD><TD>4</TD></TR><TR><TD>ctl_refresh_req</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_burstbegin</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_ready</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_wdata_req</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_rdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>ctl_rdata_valid</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_refresh_ack</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_addr_h</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>ctl_mem_addr_l</TD><TD>INPUT</TD><TD>13</TD></TR><TR><TD>ctl_mem_ba_h</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_mem_ba_l</TD><TD>INPUT</TD><TD>2</TD></TR><TR><TD>ctl_mem_cas_n_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_cas_n_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_cke_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_cke_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_cs_n_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_cs_n_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_odt_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_odt_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_ras_n_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_ras_n_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_we_n_h</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_we_n_l</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_be</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>ctl_mem_dqs_burst</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_wdata</TD><TD>INPUT</TD><TD>32</TD></TR><TR><TD>ctl_mem_wdata_valid</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_mem_rdata</TD><TD>OUTPUT</TD><TD>32</TD></TR><TR><TD>ctl_mem_rdata_valid</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>ctl_init_done</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_doing_rd</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_add_1t_ac_lat</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_add_1t_odt_lat</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_add_intermediate_regs</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_negedge_en</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>ctl_usr_mode_rdy</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_addr</TD><TD>OUTPUT</TD><TD>13</TD></TR><TR><TD>mem_ba</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_cas_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cke</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_cs_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_dm</TD><TD>OUTPUT</TD><TD>2</TD></TR><TR><TD>mem_odt</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_ras_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_we_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_reset_n</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>mem_clk</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_clk_n</TD><TD>BIDIR</TD><TD>1</TD></TR><TR><TD>mem_dq</TD><TD>BIDIR</TD><TD>16</TD></TR><TR><TD>mem_dqs</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>mem_dqsn</TD><TD>BIDIR</TD><TD>2</TD></TR><TR><TD>resynchronisation_successful</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>postamble_successful</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tracking_successful</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tracking_adjustment_up</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>tracking_adjustment_down</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>dqs_delay_ctrl_import</TD><TD>INPUT</TD><TD>6</TD></TR><TR><TD>dqs_delay_ctrl_export</TD><TD>OUTPUT</TD><TD>6</TD></TR><TR><TD>dll_reference_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_enable</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_counter_type</TD><TD>INPUT</TD><TD>4</TD></TR><TR><TD>pll_reconfig_counter_param</TD><TD>INPUT</TD><TD>3</TD></TR><TR><TD>pll_reconfig_data_in</TD><TD>INPUT</TD><TD>9</TD></TR><TR><TD>pll_reconfig_read_param</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_write_param</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig</TD><TD>INPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_clk</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_reset</TD><TD>OUTPUT</TD><TD>1</TD></TR><TR><TD>pll_reconfig_data_out</TD><TD>OUTPUT</TD><TD>9</TD></TR><TR><TD>pll_reconfig_busy</TD><TD>OUTPUT</TD><TD>1</TD></TR></TABLE></TD></TR></TD></TR></TABLE></DIV></BODY></HTML>
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