altmemddr_phy_alt_mem_phy_ciii.v

nios里面用自定义指令集来实现三角函数

    .dio_rdata_h_2x             (dio_rdata_h_2x),
    .dio_rdata_l_2x             (dio_rdata_l_2x),
    .poa_postamble_en_preset_2x (poa_postamble_en_preset_2x),
    .wdp_dm_h_2x                (wdp_dm_h_2x),
    .wdp_dm_l_2x                (wdp_dm_l_2x),
    .wdp_wdata_h_2x             (wdp_wdata_h_2x),
    .wdp_wdata_l_2x             (wdp_wdata_l_2x),
    .wdp_wdata_oe_2x            (wdp_wdata_oe_2x),
    .wdp_wdqs_2x                (wdp_wdqs_2x),
    .wdp_wdqs_oe_2x             (wdp_wdqs_oe_2x)
);


// Instance the read datapath :

//
altmemddr_phy_alt_mem_phy_read_dp_sii_ciii #(
    .ADDR_COUNT_WIDTH          (ADDR_COUNT_WIDTH),
    .BIDIR_DPINS               (BIDIR_DPINS),
    .DWIDTH_RATIO              (DWIDTH_RATIO),
    .MEM_IF_CLK_PS             (MEM_IF_CLK_PS),
    .FAMILY                    (FAMILY),
    .LOCAL_IF_DWIDTH           (LOCAL_IF_DWIDTH),
    .MEM_IF_DQ_PER_DQS         (MEM_IF_DQ_PER_DQS),
    .MEM_IF_DQS_WIDTH          (MEM_IF_DQS_WIDTH),
    .MEM_IF_DWIDTH             (MEM_IF_DWIDTH),
    .MEM_IF_PHY_NAME           (MEM_IF_PHY_NAME),
    .RDP_INITIAL_LAT           (RDP_INITIAL_LAT),
    .RDP_RESYNC_LAT_CTL_EN     (RDP_RESYNC_LAT_CTL_EN),
    .RESYNC_PIPELINE_DEPTH     (RESYNC_PIPELINE_DEPTH)
) rdp (
    .phy_clk_1x                (phy_clk_1x),
    .resync_clk_2x             (resync_clk_2x),
    .reset_phy_clk_1x_n        (reset_phy_clk_1x_n),
    .reset_resync_clk_2x_n     (reset_resync_clk_2x_n),
    .seq_rdp_dec_read_lat_1x   (seq_rdp_dec_read_lat_1x),
    .seq_rdp_dmx_swap          (seq_rdp_dmx_swap),
    .seq_rdp_inc_read_lat_1x   (seq_rdp_inc_read_lat_1x),
    .dio_rdata_h_2x            (dio_rdata_h_2x),
    .dio_rdata_l_2x            (dio_rdata_l_2x),
    .ctl_mem_rdata             (ctl_mem_rdata)
);


// Instance the write datapath :

generate

    // Half-rate Write datapath :
    if (DWIDTH_RATIO == 4)
    begin
    
        //
        altmemddr_phy_alt_mem_phy_write_dp_sii_ciii #(
                    .BIDIR_DPINS           (BIDIR_DPINS),
            .LOCAL_IF_DRATE        (LOCAL_IF_DRATE),
            .LOCAL_IF_DWIDTH       (LOCAL_IF_DWIDTH),
            .MEM_IF_DM_WIDTH       (MEM_IF_DM_WIDTH),
            .MEM_IF_DQ_PER_DQS     (MEM_IF_DQ_PER_DQS),
            .MEM_IF_DQS_WIDTH      (MEM_IF_DQS_WIDTH),
            .GENERATE_WRITE_DQS    (GENERATE_WRITE_DQS),
            .MEM_IF_DWIDTH         (MEM_IF_DWIDTH),
            .DWIDTH_RATIO          (DWIDTH_RATIO)
        ) wdp (
            .phy_clk_1x            (phy_clk_1x),
            .mem_clk_2x            (mem_clk_2x),
            .write_clk_2x          (write_clk_2x),
            .reset_phy_clk_1x_n    (reset_phy_clk_1x_n),
            .reset_mem_clk_2x_n    (reset_mem_clk_2x_n),
            .reset_write_clk_2x_n  (reset_write_clk_2x_n),
            .ctl_mem_be            (ctl_mem_be),
            .ctl_mem_dqs_burst     (ctl_mem_dqs_burst),
            .ctl_mem_wdata         (ctl_mem_wdata),
            .ctl_mem_wdata_valid   (ctl_mem_wdata_valid),
            .wdp_wdata_h_2x        (wdp_wdata_h_2x),
            .wdp_wdata_l_2x        (wdp_wdata_l_2x),
            .wdp_wdata_oe_2x       (wdp_wdata_oe_2x),
            .wdp_wdqs_2x           (wdp_wdqs_2x),
            .wdp_wdqs_oe_2x        (wdp_wdqs_oe_2x),
            .wdp_dm_h_2x           (wdp_dm_h_2x),
            .wdp_dm_l_2x           (wdp_dm_l_2x)
        );
        
    end
    
    // Full-rate :
    else
    begin
   
        //
        altmemddr_phy_alt_mem_phy_write_dp_fr_sii_ciii #(
                    .BIDIR_DPINS           (BIDIR_DPINS),
            .LOCAL_IF_DRATE        (LOCAL_IF_DRATE),
            .LOCAL_IF_DWIDTH       (LOCAL_IF_DWIDTH),
            .MEM_IF_DM_WIDTH       (MEM_IF_DM_WIDTH),
            .MEM_IF_DQ_PER_DQS     (MEM_IF_DQ_PER_DQS),
            .MEM_IF_DQS_WIDTH      (MEM_IF_DQS_WIDTH),
            .GENERATE_WRITE_DQS    (GENERATE_WRITE_DQS),
            .MEM_IF_DWIDTH         (MEM_IF_DWIDTH),
            .DWIDTH_RATIO          (DWIDTH_RATIO)
        ) wdp (
            .phy_clk_1x            (phy_clk_1x),
            .mem_clk_2x            (mem_clk_2x),
            .write_clk_2x          (write_clk_2x),
            .reset_phy_clk_1x_n    (reset_phy_clk_1x_n),
            .reset_mem_clk_2x_n    (reset_mem_clk_2x_n),
            .reset_write_clk_2x_n  (reset_write_clk_2x_n),
            .ctl_mem_be            (ctl_mem_be),
            .ctl_mem_dqs_burst     (ctl_mem_dqs_burst),
            .ctl_mem_wdata         (ctl_mem_wdata),
            .ctl_mem_wdata_valid   (ctl_mem_wdata_valid),
            .wdp_wdata_h_2x        (wdp_wdata_h_2x),
            .wdp_wdata_l_2x        (wdp_wdata_l_2x),
            .wdp_wdata_oe_2x       (wdp_wdata_oe_2x),
            .wdp_wdqs_2x           (wdp_wdqs_2x),
            .wdp_wdqs_oe_2x        (wdp_wdqs_oe_2x),
            .wdp_dm_h_2x           (wdp_dm_h_2x),
            .wdp_dm_l_2x           (wdp_dm_l_2x)
        );
        
    end
    
endgenerate

// Instance the address and command :

generate

    if (ADDR_CMD_2T_EN == 0)
    begin
    
        //
        altmemddr_phy_alt_mem_phy_addr_cmd_ciii #(
                    .DWIDTH_RATIO           (DWIDTH_RATIO),
            .MEM_ADDR_CMD_BUS_COUNT (MEM_ADDR_CMD_BUS_COUNT),
            .MEM_IF_BANKADDR_WIDTH  (MEM_IF_BANKADDR_WIDTH),
            .MEM_IF_CS_WIDTH        (MEM_IF_CS_WIDTH),
            .MEM_IF_MEMTYPE         (MEM_IF_MEMTYPE),
            .MEM_IF_ROWADDR_WIDTH   (MEM_IF_ROWADDR_WIDTH)
        ) adc (
            .ac_clk_1x                 (ac_clk_1x),
            .ac_clk_2x                 (ac_clk_2x),
            .cs_n_clk_1x               (cs_n_clk_1x),
            .cs_n_clk_2x               (cs_n_clk_2x),
            .phy_clk_1x                (phy_clk_1x),
            .reset_ac_clk_1x_n         (reset_ac_clk_1x_n),
            .reset_ac_clk_2x_n         (reset_ac_clk_2x_n),
            .reset_cs_n_clk_1x_n       (reset_cs_n_clk_1x_n),
            .reset_cs_n_clk_2x_n       (reset_cs_n_clk_2x_n),
            .ctl_add_1t_ac_lat         (ctl_add_1t_ac_lat_internal),
            .ctl_add_1t_odt_lat        (ctl_add_1t_odt_lat_internal),
            .ctl_negedge_en            (ctl_negedge_en_internal),
            .ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
            .ctl_mem_addr_h            (ctl_mem_addr_h),
            .ctl_mem_addr_l            (ctl_mem_addr_l),
            .ctl_mem_ba_h              (ctl_mem_ba_h),
            .ctl_mem_ba_l              (ctl_mem_ba_l),
            .ctl_mem_cas_n_h           (ctl_mem_cas_n_h),
            .ctl_mem_cas_n_l           (ctl_mem_cas_n_l),
            .ctl_mem_cke_h             (ctl_mem_cke_h),
            .ctl_mem_cke_l             (ctl_mem_cke_l),
            .ctl_mem_cs_n_h            (ctl_mem_cs_n_h),
            .ctl_mem_cs_n_l            (ctl_mem_cs_n_l),
            .ctl_mem_odt_h             (ctl_mem_odt_h),
            .ctl_mem_odt_l             (ctl_mem_odt_l),
            .ctl_mem_ras_n_h           (ctl_mem_ras_n_h),
            .ctl_mem_ras_n_l           (ctl_mem_ras_n_l),
            .ctl_mem_we_n_h            (ctl_mem_we_n_h),
            .ctl_mem_we_n_l            (ctl_mem_we_n_l),
            .mem_addr                  (mem_addr),
            .mem_ba                    (mem_ba),
            .mem_cas_n                 (mem_cas_n),
            .mem_cke                   (mem_cke),
            .mem_cs_n                  (mem_cs_n),
            .mem_odt                   (mem_odt),
            .mem_ras_n                 (mem_ras_n),
            .mem_we_n                  (mem_we_n)
        );

    end

    // For 2T operation, both the "_l" and "_h" inputs of the addr_cmd block are connected
    // to the "_l" controller outputs:
    else
    begin

        //
        altmemddr_phy_alt_mem_phy_addr_cmd_ciii #(
                    .DWIDTH_RATIO           (DWIDTH_RATIO),
            .MEM_ADDR_CMD_BUS_COUNT (MEM_ADDR_CMD_BUS_COUNT),
            .MEM_IF_BANKADDR_WIDTH  (MEM_IF_BANKADDR_WIDTH),
            .MEM_IF_CS_WIDTH        (MEM_IF_CS_WIDTH),
            .MEM_IF_MEMTYPE         (MEM_IF_MEMTYPE),
            .MEM_IF_ROWADDR_WIDTH   (MEM_IF_ROWADDR_WIDTH)
        ) adc (
            .ac_clk_1x                 (ac_clk_1x),
            .ac_clk_2x                 (ac_clk_2x),
            .cs_n_clk_1x               (cs_n_clk_1x),
            .cs_n_clk_2x               (cs_n_clk_2x),
            .phy_clk_1x                (phy_clk_1x),
            .reset_ac_clk_1x_n         (reset_ac_clk_1x_n),
            .reset_ac_clk_2x_n         (reset_ac_clk_2x_n),
            .reset_cs_n_clk_1x_n       (reset_cs_n_clk_1x_n),
            .reset_cs_n_clk_2x_n       (reset_cs_n_clk_2x_n),
            .ctl_add_1t_ac_lat         (ctl_add_1t_ac_lat_internal),
            .ctl_add_1t_odt_lat        (ctl_add_1t_odt_lat_internal),
            .ctl_negedge_en            (ctl_negedge_en_internal),
            .ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
            .ctl_mem_addr_h            (ctl_mem_addr_l),
            .ctl_mem_addr_l            (ctl_mem_addr_l),
            .ctl_mem_ba_h              (ctl_mem_ba_l),
            .ctl_mem_ba_l              (ctl_mem_ba_l),
            .ctl_mem_cas_n_h           (ctl_mem_cas_n_l),
            .ctl_mem_cas_n_l           (ctl_mem_cas_n_l),
            .ctl_mem_cke_h             (ctl_mem_cke_l),
            .ctl_mem_cke_l             (ctl_mem_cke_l),
            .ctl_mem_cs_n_h            ({MEM_IF_CS_WIDTH{1'b1}}),
            .ctl_mem_cs_n_l            (ctl_mem_cs_n_l),
            .ctl_mem_odt_h             (ctl_mem_odt_l),
            .ctl_mem_odt_l             (ctl_mem_odt_l),
            .ctl_mem_ras_n_h           (ctl_mem_ras_n_l),
            .ctl_mem_ras_n_l           (ctl_mem_ras_n_l),
            .ctl_mem_we_n_h            (ctl_mem_we_n_l),
            .ctl_mem_we_n_l            (ctl_mem_we_n_l),
            .mem_addr                  (mem_addr),
            .mem_ba                    (mem_ba),
            .mem_cas_n                 (mem_cas_n),
            .mem_cke                   (mem_cke),
            .mem_cs_n                  (mem_cs_n),
            .mem_odt                   (mem_odt),
            .mem_ras_n                 (mem_ras_n),
            .mem_we_n                  (mem_we_n)
        );

    end

endgenerate



// Instance the clock and reset :

//
altmemddr_phy_alt_mem_phy_clk_reset_ciii #(
    .AC_PHASE                             (AC_PHASE),
    .CLOCK_INDEX_WIDTH                    (CLOCK_INDEX_WIDTH),
    .CAPTURE_MIMIC_PATH                   (CAPTURE_MIMIC_PATH),
    .DDR_MIMIC_PATH_EN                    (DDR_MIMIC_PATH_EN),
    .DEDICATED_MEMORY_CLK_EN              (DEDICATED_MEMORY_CLK_EN),
    .DLL_EXPORT_IMPORT                    (DLL_EXPORT_IMPORT),
    .DWIDTH_RATIO                         (DWIDTH_RATIO),
    .LOCAL_IF_CLK_PS                      (LOCAL_IF_CLK_PS),
    .MEM_IF_CLK_PAIR_COUNT                (MEM_IF_CLK_PAIR_COUNT),
    .MEM_IF_CLK_PS                        (MEM_IF_CLK_PS),
    .MEM_IF_CS_WIDTH                      (MEM_IF_CS_WIDTH),
    .MEM_IF_DQ_PER_DQS                    (MEM_IF_DQ_PER_DQS),
    .MEM_IF_DQS_WIDTH                     (MEM_IF_DQS_WIDTH),
    .MEM_IF_DWIDTH                        (MEM_IF_DWIDTH),
    .MIF_FILENAME                         (MIF_FILENAME),
    .PLL_EXPORT_IMPORT                    (PLL_EXPORT_IMPORT),
    .PLL_REF_CLK_PS                       (PLL_REF_CLK_PS),
    .PLL_TYPE                             (PLL_TYPE),
    .SPEED_GRADE                          (SPEED_GRADE),
    .DLL_DELAY_BUFFER_MODE                (DLL_DELAY_BUFFER_MODE),
    .DLL_DELAY_CHAIN_LENGTH               (DLL_DELAY_CHAIN_LENGTH),
    .DQS_OUT_MODE                         (DQS_OUT_MODE),
    .DQS_PHASE                            (DQS_PHASE),
    .SCAN_CLK_DIVIDE_BY                   (SCAN_CLK_DIVIDE_BY),
    .USE_MEM_CLK_FOR_ADDR_CMD_CLK         (USE_MEM_CLK_FOR_ADDR_CMD_CLK)
) clk (
    .pll_ref_clk                          (pll_ref_clk),
    .global_reset_n                       (global_reset_n),
    .soft_reset_n                         (soft_reset_n),
    .resync_clk_1x                        (resync_clk_1x),
    .ac_clk_1x                            (ac_clk_1x),
    .ac_clk_2x                            (ac_clk_2x),
    .measure_clk_2x                       (measure_clk_2x),
    .measure_clk_1x                       (),
    .mem_clk_2x                           (mem_clk_2x),
    .mem_clk                              (mem_clk),
    .mem_clk_n                            (mem_clk_n),
    .phy_clk_1x                           (phy_clk_1x_src),
    .postamble_clk_2x                     (postamble_clk_2x),
    .resync_clk_2x                        (resync_clk_2x),
    .cs_n_clk_1x                          (cs_n_clk_1x),
    .cs_n_clk_2x                          (cs_n_clk_2x),
    .write_clk_2x                         (write_clk_2x),
    .reset_ac_clk_1x_n                    (),
    .reset_ac_clk_2x_n                    (reset_ac_clk_2x_n),
    .reset_measure_clk_2x_n               (reset_measure_clk_2x_n),
    .reset_measure_clk_1x_n               (),
    .reset_mem_clk_2x_n                   (reset_mem_clk_2x_n),
    .reset_phy_clk_1x_n                   (reset_phy_clk_1x_n),
    .reset_poa_clk_2x_n                   (reset_poa_clk_2x_n),
    .reset_resync_clk_2x_n                (reset_resync_clk_2x_n),
    .reset_resync_clk_1x_n                (),
    .reset_write_clk_2x_n                 (reset_write_clk_2x_n),
    .reset_cs_n_clk_1x_n                  (),
    .reset_cs_n_clk_2x_n                  (reset_cs_n_clk_2x_n),
    .mem_reset_n                          (mem_reset_n),
    .reset_request_n                      (reset_request_n),
    .phs_shft_busy                        (phs_shft_busy),
    .seq_pll_inc_dec_n                    (seq_pll_inc_dec_n),
    .seq_pll_select                       (seq_pll_select),
    .seq_pll_start_reconfig               (seq_pll_start_reconfig),
    .mimic_data_1x                        (),
    .mimic_data_2x                        (mimic_data)
);


// Instance the sequencer :

//
altmemddr_phy_alt_mem_phy_sequencer_wrapper
//
seq  (
    .seq_clk                            (phy_clk_1x),