📄 cycloneiii_3c25_start_niosii_standard_sopc.ptf.bak
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direction = "inout";
Is_Enabled = "1";
declare_one_bit_as_std_logic_vector = "1";
}
PORT mem_cs_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
declare_one_bit_as_std_logic_vector = "1";
}
PORT mem_cke
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
declare_one_bit_as_std_logic_vector = "1";
}
PORT mem_addr
{
type = "export";
width = "13";
direction = "output";
Is_Enabled = "1";
}
PORT mem_ba
{
type = "export";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT mem_ras_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT mem_cas_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT mem_we_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT mem_dq
{
type = "export";
width = "16";
direction = "inout";
Is_Enabled = "1";
}
PORT mem_dqs
{
type = "export";
width = "2";
direction = "inout";
Is_Enabled = "1";
}
PORT mem_dm
{
type = "export";
width = "2";
direction = "output";
Is_Enabled = "1";
}
PORT local_refresh_ack
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_wdata_req
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_init_done
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT reset_phy_clk_n
{
type = "export";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT global_reset_n
{
type = "export";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT phy_clk
{
type = "out_clk";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
}
PORT local_write_req
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_read_req
{
type = "read";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_burstbegin
{
type = "beginbursttransfer";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT local_ready
{
type = "waitrequest_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_rdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT local_rdata_valid
{
type = "readdatavalid";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT local_wdata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT local_be
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT local_size
{
type = "burstcount";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_request_n
{
type = "resetrequest_n";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "33554432";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "32";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "23";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Clock_Source = "altmemddr_phy_clk_out";
Has_Clock = "1";
MASTERED_BY altmemddr_bridge/m1
{
priority = "8";
Offset_Address = "0x00000000";
}
Base_Address = "0x02000000";
Address_Group = "0";
}
}
iss_model_name = "altera_memory";
class = "ddr_high_perf";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "Cyclone III";
datawidth = "16";
memtype = "DDR SDRAM";
local_burst_length = "1";
num_chipselects = "1";
cas_latency = "3.0";
addr_width = "23";
ba_width = "2";
row_width = "13";
col_width = "9";
clockspeed = "9090";
data_width_ratio = "2";
reg_dimm = "false";
dq_per_dqs = "8";
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Clock_Source = "osc_clk";
Has_Clock = "1";
Default_Module_Name = "altmemddr";
Required_Device_Family = "STRATIXIIGXLITE,STRATIXIIGX,STRATIXII,STRATIXIII,CYCLONEIII";
Pins_Assigned_Automatically = "1";
View
{
MESSAGES
{
}
}
}
class_version = "7.2";
SIMULATION
{
DISPLAY
{
SIGNAL a
{
name = "pll_ref_clk";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL b
{
name = "soft_reset_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL c
{
name = "global_reset_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL d
{
name = "reset_phy_clk_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL e
{
name = "reset_request_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL f
{
name = "phy_clk";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL g
{
name = "local_address";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL h
{
name = "local_size";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL i
{
name = "local_burstbegin";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL j
{
name = "local_read_req";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL k
{
name = "local_write_req";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL l
{
name = "local_ready";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL m
{
name = "local_wdata";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL n
{
name = "local_be";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL o
{
name = "local_rdata_valid";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL p
{
name = "local_rdata";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL q
{
name = "mem_clk";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL r
{
name = "mem_cs_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL s
{
name = "mem_addr";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL t
{
name = "mem_ba";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL u
{
name = "mem_ras_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL v
{
name = "mem_cas_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL w
{
name = "mem_we_n";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL x
{
name = "mem_dm";
radix = "hexadecimal";
format = "Logic";
}
SIGNAL y
{
name = "mem_dq";
radix = "hexa⌨️ 快捷键说明
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