📄 cycloneiii_3c25_start_niosii_standard_sopc.ptf.bak
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width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
visible = "0";
}
}
}
MODULE flash_ssram_tristate_bridge
{
SLAVE avalon_slave
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "1";
Register_Outgoing_Signals = "1";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY pipeline_bridge_before_atb/m1
{
priority = "1";
Offset_Address = "0x00000000";
}
Bridges_To = "tristate_master";
Base_Address = "N/A";
Has_IRQ = "0";
IRQ = "N/A";
Address_Group = "0";
}
}
MASTER tristate_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Bridges_To = "avalon_slave";
}
PORT_WIRING
{
}
MEMORY_MAP
{
Entry ext_ssram/s1
{
address = "0x01000000";
span = "0x00100000";
}
Entry ext_flash/s1
{
address = "0x00000000";
span = "0x01000000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
{
}
class = "altera_avalon_tri_state_bridge";
class_version = "7.071";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "system_clk";
Has_Clock = "1";
Instantiate_In_System_Module = "1";
Is_Bridge = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
}
MODULE ext_ssram
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
visible = "0";
}
PORT address
{
type = "address";
width = "18";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT adsc_n
{
type = "begintransfer_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT bw_n
{
type = "byteenable_n";
width = "4";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT bwe_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT chipenable1_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT data
{
type = "data";
width = "32";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT outputenable_n
{
type = "outputenable_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "0cycles";
Read_Wait_States = "0cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "1048576";
Read_Latency = "2";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Active_CS_Through_Read_Latency = "1";
Data_Width = "32";
Address_Width = "18";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY flash_ssram_tristate_bridge/tristate_master
{
priority = "8";
Offset_Address = "0x01000000";
}
Base_Address = "0x07000000";
Has_IRQ = "0";
Address_Group = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
sram_memory_size = "1";
sram_memory_units = "1048576";
ssram_data_width = "32";
ssram_read_latency = "2";
simulation_model_num_lanes = "4";
}
class = "altera_avalon_cy7c1380_ssram";
class_version = "7.071";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Clock_Source = "system_clk";
Has_Clock = "1";
Instantiate_In_System_Module = "0";
Default_Module_Name = "ssram";
Make_Memory_Model = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
iss_model_name = "altera_memory";
HDL_INFO
{
# An interface to this memory requires no additional files
# in the target project directory.
}
}
MODULE ext_flash
{
SLAVE s1
{
PORT_WIRING
{
PORT data
{
type = "data";
width = "16";
direction = "inout";
Is_Enabled = "1";
is_shared = "1";
}
PORT address
{
type = "address";
width = "23";
direction = "input";
Is_Enabled = "1";
is_shared = "1";
}
PORT read_n
{
type = "read_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
PORT select_n
{
type = "chipselect_n";
width = "1";
direction = "input";
Is_Enabled = "1";
is_shared = "0";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Write_Wait_States = "70ns";
Read_Wait_States = "70ns";
Hold_Time = "20ns";
Setup_Time = "25ns";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "1";
Address_Span = "16777216";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "1";
Active_CS_Through_Read_Latency = "0";
Data_Width = "16";
Address_Width = "23";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY flash_ssram_tristate_bridge/tristate_master
{
priority = "1";
Offset_Address = "0x00000000";
}
Base_Address = "0x06000000";
Has_IRQ = "0";
Simulation_Num_Lanes = "1";
Convert_Xs_To_0 = "1";
Address_Group = "0";
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_cfi_flash";
Supports_Flash_File_System = "1";
flash_reference_designator = "";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Setup_Value = "25";
Wait_Value = "70";
Hold_Value = "20";
Timing_Units = "ns";
Unit_Multiplier = "1";
Size = "16777216";
}
SYSTEM_BUILDER_INFO
{
Simulation_Num_Lanes = "2";
Is_Enabled = "1";
Clock_Source = "system_clk";
Has_Clock = "1";
Make_Memory_Model = "1";
Instantiate_In_System_Module = "0";
Top_Level_Ports_Are_Enumerated = "1";
View
{
MESSAGES
{
}
}
}
class = "altera_avalon_cfi_flash";
class_version = "7.071";
iss_model_name = "altera_avalon_flash";
HDL_INFO
{
}
}
MODULE altmemddr
{
PORT_WIRING
{
PORT pll_ref_clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT soft_reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT mem_clk
{
type = "export";
width = "1";
direction = "inout";
Is_Enabled = "1";
declare_one_bit_as_std_logic_vector = "1";
}
PORT mem_clk_n
{
type = "export";
width = "1";
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