📄 cycloneiii_3c25_start_niosii_standard_sopc.ptf.bak
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width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_byteenable
{
type = "byteenable";
width = "4";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess
{
type = "debugaccess";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_reset
{
type = "reset";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_resetrequest
{
type = "resetrequest";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_select
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_write
{
type = "write";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
}
}
MASTER tightly_coupled_data_master_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
PORT_WIRING
{
PORT dcm0_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_clken
{
type = "clken";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT dcm0_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT dcm0_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry onchip_ram/s2
{
address = "0x09010000";
span = "0x00008000";
}
}
}
MASTER data_master
{
SYSTEM_BUILDER_INFO
{
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Data_Master = "1";
Address_Group = "0";
Is_Readable = "1";
Is_Writeable = "1";
Interrupt_Range = "0-31";
}
PORT_WIRING
{
PORT d_irq
{
type = "irq";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT d_byteenable
{
type = "byteenable";
width = "4";
direction = "output";
Is_Enabled = "1";
}
PORT d_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT d_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT d_write
{
type = "write";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT d_writedata
{
type = "writedata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT jtag_debug_module_debugaccess_to_roms
{
type = "debugaccess";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry altmemddr_bridge/s1
{
address = "0x02000000";
span = "0x02000000";
}
Entry altmemddr/s1
{
address = "0x02000000";
span = "0x02000000";
}
Entry pipeline_bridge_peripherals/s1
{
address = "0x08000000";
span = "0x00000100";
}
Entry jtag_uart/avalon_jtag_slave
{
address = "0x08000080";
span = "0x00000008";
}
Entry button_pio/s1
{
address = "0x08000060";
span = "0x00000010";
}
Entry sys_clk_timer/s1
{
address = "0x08000000";
span = "0x00000020";
}
Entry high_res_timer/s1
{
address = "0x08000020";
span = "0x00000020";
}
Entry led_pio/s1
{
address = "0x08000070";
span = "0x00000010";
}
Entry sysid/control_slave
{
address = "0x08000088";
span = "0x00000008";
}
Entry sys_pll/s1
{
address = "0x08000040";
span = "0x00000020";
}
Entry cpu/jtag_debug_module
{
address = "0x09008800";
span = "0x00000800";
}
Entry pipeline_bridge_before_atb/s1
{
address = "0x06000000";
span = "0x02000000";
}
Entry ext_ssram/s1
{
address = "0x07000000";
span = "0x00100000";
}
Entry ext_flash/s1
{
address = "0x06000000";
span = "0x01000000";
}
}
}
MASTER tightly_coupled_instruction_master_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
PORT_WIRING
{
PORT icm0_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT icm0_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT icm0_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT icm0_clken
{
type = "clken";
width = "1";
direction = "output";
Is_Enabled = "1";
}
}
MEMORY_MAP
{
Entry onchip_ram/s1
{
address = "0x09010000";
span = "0x00008000";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
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