📄 cycloneiii_3c25_start_niosii_standard_sopc.ptf.bak
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SYSTEM cycloneIII_3c25_start_niosII_standard_sopc
{
System_Wizard_Version = "7.20";
System_Wizard_Build = "175";
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2008.03.16.16:36:02
#
# clock_source "osc_clk"
# altera_nios2 "cpu"
# altera_avalon_tri_state_bridge "flash_ssram_tristate_bridge"
# altera_avalon_cy7c1380_ssram "ext_ssram"
# altera_avalon_cfi_flash "ext_flash"
# altmemddr "altmemddr"
# altera_avalon_clock_crossing "altmemddr_bridge"
# altera_avalon_pipeline_bridge "pipeline_bridge_peripherals"
# altera_avalon_jtag_uart "jtag_uart"
# altera_avalon_pio "button_pio"
# altera_avalon_timer "sys_clk_timer"
# altera_avalon_timer "high_res_timer"
# altera_avalon_onchip_memory2 "onchip_ram"
# altera_avalon_pio "led_pio"
# altera_avalon_sysid "sysid"
# altera_avalon_pll "sys_pll"
# altera_avalon_pipeline_bridge "pipeline_bridge_before_atb"
# SPDP_CAST_COMP "cpu_SPDP_CAST_COMP_inst"
#
# Contains 43 connections.
#
Builder_Application = "sopc_builder_ca";
#. values for Builder_Application are:
#. sopc_builder_preview --> 6.1p, 7.0p prerelease versions
#. sopc_builder_ca --> 7.1 and later
#. (missing) --> 6.0 or earlier
WIZARD_SCRIPT_ARGUMENTS
{
hdl_language = "verilog";
device_family = "CYCLONEIII";
device_family_id = "CYCLONEIII";
generate_sdk = "0";
do_build_sim = "0";
hardcopy_compatible = "0";
CLOCKS
{
CLOCK osc_clk
{
frequency = "50000000";
source = "External";
Is_Clock_Source = "0";
display_name = "osc_clk";
pipeline = "0";
clock_module_connection_point_for_c2h = "osc_clk.clk";
}
CLOCK altmemddr_phy_clk
{
frequency = "110000000";
source = "";
Is_Clock_Source = "1";
display_name = "phy_clk from altmemddr";
pipeline = "0";
clock_module_connection_point_for_c2h = "altmemddr.sysclk";
}
CLOCK altmemddr_phy_clk_out
{
frequency = "110000000";
source = "altmemddr_phy_clk";
Is_Clock_Source = "0";
display_name = "altmemddr_phy_clk_out";
}
CLOCK sys_pll_c0
{
frequency = "100000000";
source = "";
Is_Clock_Source = "1";
display_name = "c0 from sys_pll";
pipeline = "0";
clock_module_connection_point_for_c2h = "sys_pll.c0";
}
CLOCK system_clk
{
frequency = "100000000";
source = "sys_pll_c0";
Is_Clock_Source = "0";
display_name = "system_clk";
}
CLOCK sys_pll_c1
{
frequency = "100000000";
source = "";
Is_Clock_Source = "1";
display_name = "c1 from sys_pll";
pipeline = "0";
clock_module_connection_point_for_c2h = "sys_pll.c1";
}
CLOCK ssram_clk
{
frequency = "100000000";
source = "sys_pll_c1";
Is_Clock_Source = "0";
display_name = "ssram_clk";
}
}
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
board_class = "";
view_master_columns = "1";
view_master_priorities = "0";
generate_hdl = "";
bustype_column_width = "0";
clock_column_width = "80";
name_column_width = "75";
desc_column_width = "75";
base_column_width = "75";
end_column_width = "75";
BOARD_INFO
{
altera_avalon_cfi_flash
{
reference_designators = "";
}
}
}
MODULE cpu
{
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_address
{
type = "address";
width = "28";
direction = "output";
Is_Enabled = "1";
}
PORT i_read
{
type = "read";
width = "1";
direction = "output";
Is_Enabled = "1";
}
PORT i_readdata
{
type = "readdata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT i_readdatavalid
{
type = "readdatavalid";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT i_waitrequest
{
type = "waitrequest";
width = "1";
direction = "input";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Asynchronous = "0";
DBS_Big_Endian = "0";
Adapts_To = "";
Do_Stream_Reads = "0";
Do_Stream_Writes = "0";
Max_Address_Width = "32";
Data_Width = "32";
Address_Width = "28";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "";
Linewrap_Bursts = "";
Burst_On_Burst_Boundaries_Only = "";
Always_Burst_Max_Burst = "";
Is_Big_Endian = "0";
Is_Enabled = "1";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
}
MEMORY_MAP
{
Entry altmemddr_bridge/s1
{
address = "0x02000000";
span = "0x02000000";
}
Entry altmemddr/s1
{
address = "0x02000000";
span = "0x02000000";
}
Entry cpu/jtag_debug_module
{
address = "0x09008800";
span = "0x00000800";
}
Entry pipeline_bridge_before_atb/s1
{
address = "0x06000000";
span = "0x02000000";
}
Entry ext_ssram/s1
{
address = "0x07000000";
span = "0x00100000";
}
Entry ext_flash/s1
{
address = "0x06000000";
span = "0x01000000";
}
}
}
MASTER custom_instruction_master
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Is_Custom_Instruction = "1";
Is_Enabled = "1";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
}
PORT_WIRING
{
PORT dataa
{
type = "dataa";
width = "32";
direction = "output";
}
PORT datab
{
type = "datab";
width = "32";
direction = "output";
}
PORT result
{
type = "result";
width = "32";
direction = "input";
}
PORT clk_en
{
type = "clk_en";
width = "1";
direction = "output";
}
PORT reset
{
type = "reset";
width = "1";
direction = "output";
}
PORT start
{
type = "start";
width = "1";
direction = "output";
}
PORT done
{
type = "done";
width = "1";
direction = "input";
}
PORT n
{
type = "n";
width = "8";
direction = "output";
}
PORT a
{
type = "a";
width = "5";
direction = "output";
}
PORT b
{
type = "b";
width = "5";
direction = "output";
}
PORT c
{
type = "c";
width = "5";
direction = "output";
}
PORT readra
{
type = "readra";
width = "1";
direction = "output";
}
PORT readrb
{
type = "readrb";
width = "1";
direction = "output";
}
PORT writerc
{
type = "writerc";
width = "1";
direction = "output";
}
}
}
SLAVE jtag_debug_module
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Address_Span = "2048";
Read_Latency = "0";
Is_Memory_Device = "1";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "9";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
Accepts_External_Connections = "1";
Requires_Internal_Connections = "";
MASTERED_BY cpu/instruction_master
{
priority = "1";
Offset_Address = "0x09008800";
}
MASTERED_BY cpu/data_master
{
priority = "1";
Offset_Address = "0x09008800";
}
Base_Address = "0x09008800";
Is_Readable = "1";
Is_Writeable = "1";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "0";
Address_Group = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT jtag_debug_module_address
{
type = "address";
width = "9";
direction = "input";
Is_Enabled = "1";
}
PORT jtag_debug_module_begintransfer
{
type = "begintransfer";
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