altmemddr_phy_ddr_timing.sdc

nios里面用自定义指令集来实现三角函数

## This file constrains the auto-calibrating memory interface
## You may need to edit the parameters at the top of this file
## to match your memory device.
## Generated by:7.2
set t(period) 9.090
set t(board_skew) 0.020
set t(DS) 0.400
set t(DH) 0.400
set t(AC) 0.700
set t(IS) 0.600
set t(IH) 0.600
set t(DSS) 0.2
set t(DSH) 0.2
set t(DQSS) 0.28
set t(DQSQ) 0.400
set t(QHS) 0.500
set t(DQSCK) 0.550
set t(capture_shift) 2.2
set t(resync_shift) 2.872
set t(HP) 4.091
if {$::TimeQuestInfo(family) == "Arria GX"} {
set t(mimic_shift) 2.200
} elseif {$::TimeQuestInfo(family) == "HardCopy II"} {
set t(mimic_shift) 2.000
} elseif {$::TimeQuestInfo(family) == "Cyclone III"} {
set t(mimic_shift) 2.500
} else {
set t(mimic_shift) 1.600
}
set t(calibration_error) 1.144
set t(additional_addresscmd_tpd) 0.000
set corename "altmemddr_phy"
set t(inclk_period) 20.000
set t(DCD_total) 0.250
set t(PLL_PSERR) 0.060
##
##Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
##use of Altera Corporation's design tools, logic functions and other
##software and tools, and its AMPP partner logic functions, and any
##output files any of the foregoing (including device programming or
##simulation files), and any associated documentation or information are
##expressly subject to the terms and conditions of the Altera Program
##License Subscription Agreement or other applicable license agreement,
##including, without limitation, that your use is for the sole purpose
##of programming logic devices manufactured by Altera and sold by Altera
##or its authorized distributors. Please refer to the applicable
##agreement for further details.
proc ddr_pin {n pin pins_array_name} {
  upvar 1 $pins_array_name pins
  global pins
  #puts "ddr_pin $n $pin $pins_array_name"
  if {![info exists pins($n)] } {
    post_message -type critical_warning "ddr_pin $n $pin $pins_array_name didn't recognise '$n' as a pin type"
  } else {
    lappend pins($n) $pin
  }
}
set pin_file_name "altmemddr_phy_ddr_pins.tcl"
set dirname [file dirname [info script]] 
set fn [file join $dirname $pin_file_name]
source $fn

proc add_requirements_for_instance {corename instance_name t_name altmemddr_phy_use_high_performance_timing} {
upvar 1 $t_name t
set instname "${instance_name}|${corename}"
global ck_output_clocks
array unset ck_output_clocks
global pins
array unset pins
set pins(ck_p) [list]
set pins(ck_n) [list]
set pins(addrcmd) [list]
set pins(addrcmd_2t) [list]
set pins(dqsgroup) [list]
set pins(dgroup) [list]


get_ddr_pins $instname pins
set msg_list [list]
set ck_pll_clock_id [get_output_clock_id $pins(ck_p) "CK output" msg_list]
if {$ck_pll_clock_id == -1} {
  foreach {msg_type msg} $msg_list {
    post_message -type $msg_type "altmemddr_phy_ddr_timing.sdc: $msg"
  }
  post_message -type warning "altmemddr_phy_ddr_timing.sdc: Failed to find PLL clock for pins [join $pins(ck_p)]"
} else {
  set ck_pll_clock [get_node_info -name $ck_pll_clock_id]
  set pll_ref_clk_id [get_input_clk_id $ck_pll_clock_id]
  if {$pll_ref_clk_id != -1} {
    set pll_ref_clk [get_node_info -name $pll_ref_clk_id]
    if {[get_collection_size [get_clocks $pll_ref_clk]] == 0} {
      create_clock -period $t(inclk_period) $pll_ref_clk
    }

    if {[get_collection_size [get_clocks $ck_pll_clock]] > 0} {
      # PLL clocks already derived
    } else {
      derive_pll_clocks
    }
  } else {
    post_message -type critical_warning "altmemddr_phy_ddr_timing.sdc: Failed to find PLL input clock pin driving $ck_pll_clock"
  }
}

set resync_clock_pattern ${instname}_alt_mem_phy_ciii_inst|clk|*|altpll_component|auto_generated|pll1|clk\[3\]
set resync_clock_id ""
sett_collection resync_clock_id [get_pins -compatibility_mode $resync_clock_pattern]
set resync_clock [get_node_info -name $resync_clock_id]
set resync_pll_ref_clk_id [get_input_clk_id $resync_clock_id]
if {$resync_pll_ref_clk_id != -1} {
  set resync_pll_ref_clk [get_node_info -name $resync_pll_ref_clk_id]
  if {[get_collection_size [get_clocks $resync_pll_ref_clk]] == 0} {
    create_clock -period $t(inclk_period) $resync_pll_ref_clk
  }
} else {
  post_message -type warning "altmemddr_phy_ddr_timing.sdc: Failed to find PLL input clock pin driving $resync_clock"
}
set mimic_clock_pattern ${instname}_alt_mem_phy_ciii_inst|clk|*|altpll_component|auto_generated|pll1|clk\[4\]
set mimic_clock_pins [get_pins -compatibility_mode $mimic_clock_pattern]
if {[get_collection_size $mimic_clock_pins] == 1} {
  set mimic_clock_id ""
  sett_collection mimic_clock_id $mimic_clock_pins
  set mimic_clock [get_node_info -name $mimic_clock_id]
} else {
  set mimic_clock ""
}
set system_clock_pattern ${instname}_alt_mem_phy_ciii_inst|clk|*|altpll_component|auto_generated|pll1|clk\[1\]
set system_clock_pins [get_pins -compatibility_mode $system_clock_pattern]
if {[get_collection_size $system_clock_pins] == 1} {
  set system_clock_id ""
  sett_collection system_clock_id $system_clock_pins
  set system_clock [get_node_info -name $system_clock_id]
  set_false_path -from $pll_ref_clk -to $system_clock
  set_false_path -to $pll_ref_clk -from $system_clock
} else {
  set system_clock ""
}
# Not QDR datapath.
set dirname [file dirname [info script]] 
set fn [file join $dirname ${corename}_cu.tcl]
if { $::TimeQuestInfo(family) == "HardCopy II" &&  [file exists $fn]} {
  source [file join $dirname $fn]
  foreach s [list fpga_tREAD_CAPTURE_SETUP_ERROR fpga_tREAD_CAPTURE_HOLD_ERROR fpga_RESYNC_SETUP_ERROR fpga_RESYNC_HOLD_ERROR fpga_PA_DQS_SETUP_ERROR fpga_PA_DQS_HOLD_ERROR WR_DQS_DQ_SETUP_ERROR WR_DQS_DQ_HOLD_ERROR fpga_tCK_ADDR_CTRL_SETUP_ERROR fpga_tCK_ADDR_CTRL_HOLD_ERROR fpga_tDQSS_SETUP_ERROR fpga_tDQSS_HOLD_ERROR fpga_tDSSH_SETUP_ERROR fpga_tDSSH_HOLD_ERROR] {
    if { ! [info exists $s] } {
      post_message -type critical_warning "ALTMEMPHY: Missing setting in $fn:$s"
    }
  }
} else {
  if { $::TimeQuestInfo(family) == "HardCopy II" } {
    if { $::TimeQuestInfo(nameofexecutable) != "quartus_fit"} {
      post_message -type warning "HardCopy II clock uncertainty file $fn could not be found"
    }
  }
set fpga_tREAD_CAPTURE_SETUP_ERROR 0
set fpga_tREAD_CAPTURE_HOLD_ERROR 0
set fpga_RESYNC_SETUP_ERROR 0
set fpga_RESYNC_HOLD_ERROR 0
set fpga_PA_DQS_SETUP_ERROR 0
set fpga_PA_DQS_HOLD_ERROR 0
set WR_DQS_DQ_SETUP_ERROR 0
set WR_DQS_DQ_HOLD_ERROR 0
set fpga_tCK_ADDR_CTRL_SETUP_ERROR 0
set fpga_tCK_ADDR_CTRL_HOLD_ERROR 0
set fpga_tDQSS_SETUP_ERROR 0
set fpga_tDQSS_HOLD_ERROR 0
set fpga_tDSSH_SETUP_ERROR 0
set fpga_tDSSH_HOLD_ERROR 0
}
# post_message -type info "Creating CK output clocks"
set ck_clock_types_list [list tDSS tDQSS ac_rise ac_fall]
set source $ck_pll_clock
foreach ckpin [concat $pins(ck_p) $pins(ck_n)] {
  if { [lsearch -exact $pins(ck_p) $ckpin] != -1 } { 
    set invert ""
    set ckpn p
  } elseif { [lsearch -exact $pins(ck_n) $ckpin] != -1 } {
    set invert -invert
    set ckpn n
  } else {
    error "Can't find pin $ckpin in $pins(ck_p) or $pins(ck_n)"
  }
  # We don't care about the tco of the memory clocks
  set_false_path -from * -to [get_ports $ckpin]
  set clocknamestub "${instname}_ck_${ckpn}_${ckpin}"
  foreach ck_clock_type $ck_clock_types_list {
    set clockname "${clocknamestub}_${ck_clock_type}"
    create_generated_clock -add -multiply_by 1 -source $source -master_clock $source $invert -name $clockname $ckpin
    add_output_clock $ck_clock_type $ckpn $clockname
  }