alt_cusp72_muxbin2_wire.vhd

来自「nios里面用自定义指令集来实现三角函数」· VHDL 代码 · 共 40 行

-- alt_cusp72_muxbin2_wire.vhd

library ieee, altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use altera.alt_cusp72_package.all;

entity alt_cusp72_muxbin2_wire is
    generic (
        NAME    : string := "";
        PORTS   : integer := 2;
        WIDTH   : integer := 1
    );
    port (
        sel     : in  std_logic := '0';
        data0   : in  std_logic := '0';
        data1   : in  std_logic := '0';
        q       : out std_logic
    );
end entity;


architecture rtl of alt_cusp72_muxbin2_wire is
begin
    assert WIDTH = 1
        report "WIDTH generic must be 1 for wire muxes"
        severity ERROR;

    assert PORTS <= 2
        report "PORTS generic must be 2 or less"
        severity ERROR;

with sel select
    q <= data0   when '0',
         data1   when '1',
         'X'     when others;

end architecture;